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Toward on-chip datacenters: a perspective on general trends and on-chip particulars

Published: 01 October 2012 Publication History

Abstract

Due to economical reasons, the traditional philosophy in data centers was to scale out, rather than scaling up. However, the advances in CMP technology enabled chip multiprocessors to become more prevalent and they are expected to become more affordable and power-efficient in the coming years. Current trend towards more densely packaged systems and increasing demand for higher performance push the market towards placing datacenters on highly powerful chips that have many cores on a single platform. However, increasing the number of cores on a single chip brings along very important problems to be addressed at the chip level regarding the use of shared resources and QoS satisfaction. After briefly exploring current datacenter perspective, this paper captures the current state of the art in the field of chip multiprocessors through a detailed discussion of different studies that pave the way to the datacenters on-chip. Finally, a number of open research issues are highlighted with the intention of inspiring new contributions and developments in the field of datacenters on-chip.

References

[1]
Al-Fares M, Loukissas A, Vahdat A (2008) A scalable, commodity data center network architecture. In: ACM SIGCOMM, pp 63-74.
[2]
Barroso L, Holzle U (2007) The case for energy-proportional computing. Computer 33-37.
[3]
Barroso L, Holzle U (2009) The datacenter as a computer: an introduction to the design of warehousescale machines. Synth Lect Comput Archit 4(1):1-108.
[4]
Bianchini R, Rajamony R (2004) Power and energy management for server systems. Computer 68-76.
[5]
Bitirgen R, Ipek E, Martinez J (2008) Coordinated management of multiple interacting resources in chip multiprocessors: a machine learning approach. In: MICRO, pp 318-329.
[6]
Blackburn M (2008) Five ways to reduce data center power consumption. The Green Grid. http:// www.thegreengrid.org/Global/Content/white-papers/Five-Ways-to-Save-Power.
[7]
Building a reliable and dynamic data center with PAN manager software (2009) Egenera Inc.
[8]
Buyya R et al (2009) Cloud computing and emerging IT platforms: vision, hype, and reality for delivering computing as the 5th utility. Future Gener Comput Syst 25(6):599-616.
[9]
Chang J, Sohi G (2007) Cooperative cache partitioning for chip multiprocessors. In: ICS, p 252.
[10]
Cisco (2009) Trade association. In: InfiniBand TM architecture specification volume.
[11]
Coskun A, Strong R, Tullsen D, Rosing T (2009) Evaluating the impact of job scheduling and power management on processor lifetime for chip multiprocessors. In: International joint conference on measurement and modeling of computer systems, pp 169-180.
[12]
Das R, Mutlu O, Moscibroda T, Das C, (2009) Application-aware prioritization mechanisms for onchip networks. In: MICRO.
[13]
Energy efficient infrastructures for data centers (2007) Fujitsu Siemens Computers and Knurr.
[14]
Franceschini MM, Lastras-Montano LA, Qureshi MK, Srinivasan V (2009) Iterative write pausing techniques to improve read latency of memory systems. US Patent Appl 12/533,548, Jul 31, 2009.
[15]
Greenberg A, Hamilton J, Maltz D, Patel P (2008a) The cost of a cloud: research problems in data center networks. Comput Commun Rev 39(1):68-73.
[16]
Greenberg A, Lahiri P, Maltz D, Patel P, Sengupta S (2008b) Towards a next generation data center architecture: scalability and commoditization. In: Workshop on programmable routers for extensible services of tomorrow. ACM Press, New York, pp 57-62.
[17]
Grot B, Keckler S, Mutlu O (2009) Preemptive virtual clock: a flexible, efficient, and cost-effective QoS scheme for networks-on-chip. In: MICRO.
[18]
Gunther S, Binns F, Carmean D, Hall J (2001) Managing the impact of increasing microprocessor power consumption. Intel Technol J 1:1-9.
[19]
Herdrich A et al (2009) Rate-based QoS techniques for cache/memory in CMP platforms. In: ICS, pp 479-488.
[20]
Intel (2009) Intel chip chat. http://www.intel.com/design/chipchat.htm.
[21]
Isci C et al (2006) An analysis of efficient multi-core global power management policies: maximizing performance for a given power budget. In: MICRO, pp 347-358.
[22]
Iyer R et al (2007) Datacenter-on-chip architectures: tera-scale opportunities and challenges. Intel Technol J 11(3):227-238.
[23]
Iyer R et al (2009) VM3: measuring, modeling and managing VM shared tesources. Comput Netw
[24]
Kim C, Burger D, Keckler S (2002) An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches. ACM SIGPLAN Not 37(10):222.
[25]
Kim S, Chandra D, Solihin Y (2004) Fair cache sharing and partitioning in a chip multiprocessor architecture. In: PACT, pp 111-122.
[26]
Kim Y, Han D, Mutlu O, Harchol Balter M (2009) ATLAS: a scalable and high performance scheduling algorithm for multiple memory controllers. In: HPCA.
[27]
Lim K et al (2008) Understanding and designing new server architectures for emerging warehouse-computing environments. In: ISCA, pp 315-326.
[28]
Manne S, Klauser A, Grunwald D (1998) Pipeline gating: speculation control for energy reduction. In: ISCA, vol 25, pp 132-141.
[29]
Meeting the DC power and cooling challenge (2008) Sun Microsystems Professional Series: Gartner Report.
[30]
Merino J, Puente V, Prieto P, Gregorio J (2008) SP-NUCA: a cost effective dynamic non-uniform cache architecture. Comput Archit News 36(2):64-71.
[31]
Moore J, Chase J, Farkas K, Ranganathan P (2005) Data center workload monitoring, analysis, and emulation. In: Eighth workshop on computer architecture evaluation using commercial workloads.
[32]
Moore J, Chase J, Ranganathan P, Sharma R (2005) Making scheduling "cool": temperature-aware workload placement in data centers. In: USENIX.
[33]
Mukherjee T et al (2007) Software architecture for dynamic thermal management in datacenters. In: COMSWARE.
[34]
Mutlu O, Moscibroda T (2007) Stall-time fair memory access scheduling for chip multiprocessors. In: MICRO, pp 146-160.
[35]
Mutlu O, Moscibroda T (2008) Parallelism-aware batch scheduling: enhancing both performance and fairness of shared DRAM systems. In: ISCA.
[36]
Nesbit K, Aggarwal N, Laudon J, Smith J (2006) Fair queuing memory systems. In: MICRO, pp 208- 222.
[37]
Nesbit K et al (2008) Multicore resource management. IEEE MICRO 28(3):6-16.
[38]
Patel C (2003) A vision of energy aware computing from chips to data centers. In: International symposium on micro-mechanical engineering.
[39]
Powell M, Schuchman E, Vijaykumar T (2005) Balancing resource utilization to mitigate power density in processor pipelines. In: MICRO, p 304.
[40]
Qureshi M (2009) Adaptive spill-receive for robust high-performance caching in CMPs. In: HPCA, pp 45-54.
[41]
Ramos L, Bianchini R (2008) C-Oracle: predictive thermal management for data centers. In: HPCA.
[42]
Rangan K, Wei G, Brooks D (2009) Thread motion: fine-grained power management for multicore systems. Comput Archit News 37(3):302-313.
[43]
Ranganathan P (2011) From microprocessors to nanostores: rethinking data-centric systems. Computer 44(1):39-48.
[44]
Verma A, Dasgupta G, Nayak T, De P, Kothari R (2009) Server workload analysis for power minimization using consolidation. In: Usenix ATC.
[45]
Virtualizing data center memory for performance and efficiency (2008) Mellanox Technologies.
[46]
Walsh W, Tesauro G, Kephart J, Das R, (2004) Utility functions in autonomic systems. In: International conference on autonomic computing, pp 70-77.
[47]
Wulf W, McKee S (1995) Hitting the memory wall: implications of the obvious. Comput Archit News 23(1):20-24.

Cited By

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  • (2024)High-performance application mapping in network-on-chip-based multicore systemsThe Journal of Supercomputing10.1007/s11227-024-06184-980:13(18573-18599)Online publication date: 1-Sep-2024
  • (2023)Machine Learning Enabled Solutions for Design and Optimization Challenges in Networks-on-Chip based Multi/Many-Core ArchitecturesACM Journal on Emerging Technologies in Computing Systems10.1145/359147019:3(1-26)Online publication date: 30-Jun-2023
  • (2012)Measuring interference between live datacenter applicationsProceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis10.5555/2388996.2389066(1-12)Online publication date: 10-Nov-2012

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Information

Published In

cover image The Journal of Supercomputing
The Journal of Supercomputing  Volume 62, Issue 1
October 2012
616 pages

Publisher

Kluwer Academic Publishers

United States

Publication History

Published: 01 October 2012

Author Tags

  1. Chip multi-processor
  2. Datacenter
  3. Power management
  4. Resource sharing

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View all
  • (2024)High-performance application mapping in network-on-chip-based multicore systemsThe Journal of Supercomputing10.1007/s11227-024-06184-980:13(18573-18599)Online publication date: 1-Sep-2024
  • (2023)Machine Learning Enabled Solutions for Design and Optimization Challenges in Networks-on-Chip based Multi/Many-Core ArchitecturesACM Journal on Emerging Technologies in Computing Systems10.1145/359147019:3(1-26)Online publication date: 30-Jun-2023
  • (2012)Measuring interference between live datacenter applicationsProceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis10.5555/2388996.2389066(1-12)Online publication date: 10-Nov-2012

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