Article

20.2 New Techniques for Deterministic Test Pattern Generation

Authors:

J. H. PatelAuthors Info & Claims

VTS '98: Proceedings of the 16th IEEE VLSI Test Symposium

Page 446

Published: 26 April 1998 Publication History

Abstract

This paper presents new techniques for speeding up deterministic test pattern generation for VLSI circuits. These techniques improve the PODEM algorithm by reducing number of backtracks with a low computational cost. This is achieved by finding more necessary signal line assignments, by detecting conflicts earlier, and by avoiding unnecessary work during test generation. We have incorporated these techniques into an ATPG system for combinational circuits, called ATOM. The performance results for the ISCAS85 and full scan version of the ISCAS89 benchmark circuits demonstrated the effectiveness of these techniques on the test generation performance.

References

[1]

M. Abramovici, J. J. Kulikowski, P. R. Menon, and D. T. Miller, "SMART and FAST: Test generation for VLSI scan-design circuits", IEEE Design and Test of Computers , pp 43-54, August 1986.

[2]

F. Brglez and H. Fujiwara, "A Neutral Netlist of 10 Combinational Benchmark Designs and a Special Translator in Fortran", in Proc. of the Int. Symp. on Circuits and Systems , June 1985.

[3]

F. Brglez, D. Bryan, and K. Kozminski, "Combinational Profiles of Sequential Benchmark Circuits", in Proc. of the Int. Symp. on Circuits and Systems , pp. 1929-1934, May 1989.

[4]

H. Fujiwara and S. Toida, "The complexity of fault detection problems for combinational logic circuits", IEEE Trans. on Computers , pp. 555-560, June 1982.

[5]

H. Fujiwara and T. Shimono, "On the acceleration of test generation algorithms", IEEE Trans. on Computers , pp. 1137-1144, December 1983.

[6]

P. Goel, "An implicit enumeration algorithm to generate tests for combinational logic circuits", IEEE Trans. on Computers , pp. 21-222, March 1981.

[7]

T. Kirkland and M. R. Mercer, "A topological search algorithm for ATPG", in Proc. of the Design Automation Conf. , pp. 502-508, June 1987.

[8]

S. Kundu, L. M. Huisman, I. Nair, V. Iyengar, and L. N. Reddy, "A Small Test Generator for Large Designs", Proc. of the Int. Test Conf. , pp. 30-40, September 1992.

[9]

W. Kunz and D. Pradhan, "Recursive Learning: An Attractive Alternative to the Decision Tree for Test Generation in Digital Circuits", Proc. of the Int. Test Conf. , pp. 816-825, September 1992.

[10]

T. Larrabee, "Test Pattern Generation Using Boolean Satisfiability", IEEE Trans. on Computer-Aided Design , pp. 4-15, January 1992.

[11]

T. H. Niermann, W. Cheng, and J. H. Patel, "PROOFS: A fast, memory-efficient sequential circuit fault simulator", IEEE Trans. on Computer-Aided Design , pp. 198-207, February 1992.

[12]

M. H. Schulz, E. Trischler, and T. M. Sarfert, "SOCRATES: A highly efficient automatic test pattern generation system", IEEE Trans. on Computer-Aided Design , pp. 126-137, January 1988.

[13]

M. H. Schulz and E. Auth, "Improved deterministic test pattern generation with applications to redundancy identification", IEEE Trans. on Computer-Aided Design , pp. 811-816, July 1989.

[14]

J. P. M. Silva and K. A. Sakallah, "Dynamic Search-Space Pruning Techniques in Path Sensitization", in Proc. of the Design Automation Conf. , pp. 705-711, June 1994.

[15]

J. P. M. Silva and K. A. Sakallah, "Robust Search Algorithms for Test Pattern Generation", in Proc. of the Fault-Tolerant Computing Symp. , pp. 152-161, June 1997.

[16]

P. Stephan, R. K. Brayton and A. L. Sagiovanni-Vincentelli, "Combinational Test Generation Using Satisfiability", In IEEE Trans. on Computer-Aided Design , pp. 1167-1176, September 1996.

[17]

J. A. Waicukauski, P. A. Shupe, D. J. Giramma, and A. Matin, "ATPG for Ultra-Large Structured Designs", in Proc. of the Int. Test Conf. , pp. 44-51, August 1990.

Cited By

Chandrasekar MRahagude NHsiao M(2010)Search State Compatibility Based Incremental Learning Framework and Output Deviation Based X-filling for Diagnostic Test GenerationJournal of Electronic Testing: Theory and Applications10.1007/s10836-010-5142-226:2(165-176)Online publication date: 1-Apr-2010
https://dl.acm.org/doi/10.1007/s10836-010-5142-2
Elm MWunderlich HImhof MZoellin CLeenstra JMaeding NFix L(2008)Scan chain clustering for test power reductionProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391680(828-833)Online publication date: 8-Jun-2008
https://dl.acm.org/doi/10.1145/1391469.1391680
Imhof MZoellin CWunderlich HMaeding NLeenstra JLevitan S(2007)Scan test planning for power reductionProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278614(521-526)Online publication date: 4-Jun-2007
https://dl.acm.org/doi/10.1145/1278480.1278614
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Index Terms

20.2 New Techniques for Deterministic Test Pattern Generation
1. Hardware

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cover image Guide Proceedings

VTS '98: Proceedings of the 16th IEEE VLSI Test Symposium

April 1998

ISBN:0818684364

Copyright © Copyright © 1998 IEEE. All Rights Reserved.

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IEEE Computer Society

United States

Publication History

Published: 26 April 1998

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Cited By

Chandrasekar MRahagude NHsiao M(2010)Search State Compatibility Based Incremental Learning Framework and Output Deviation Based X-filling for Diagnostic Test GenerationJournal of Electronic Testing: Theory and Applications10.1007/s10836-010-5142-226:2(165-176)Online publication date: 1-Apr-2010
https://dl.acm.org/doi/10.1007/s10836-010-5142-2
Elm MWunderlich HImhof MZoellin CLeenstra JMaeding NFix L(2008)Scan chain clustering for test power reductionProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391680(828-833)Online publication date: 8-Jun-2008
https://dl.acm.org/doi/10.1145/1391469.1391680
Imhof MZoellin CWunderlich HMaeding NLeenstra JLevitan S(2007)Scan test planning for power reductionProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278614(521-526)Online publication date: 4-Jun-2007
https://dl.acm.org/doi/10.1145/1278480.1278614
Sharifi SJaffari JHosseinabady MAfzali-Kusha ANavabi Z(2005)Simultaneous Reduction of Dynamic and Static Power in Scan StructuresProceedings of the conference on Design, Automation and Test in Europe - Volume 210.1109/DATE.2005.270(846-851)Online publication date: 7-Mar-2005
https://dl.acm.org/doi/10.1109/DATE.2005.270
Wong JPotkonjak M(2004)Relative generic computational forensic techniquesProceedings of the 6th international conference on Information Hiding10.1007/978-3-540-30114-1_11(148-163)Online publication date: 23-May-2004
https://dl.acm.org/doi/10.1007/978-3-540-30114-1_11
Sheng SHsiao M(2003)Efficient Preimage Computation Using A Novel Success-Driven ATPGProceedings of the conference on Design, Automation and Test in Europe - Volume 110.5555/789083.1022826Online publication date: 3-Mar-2003
https://dl.acm.org/doi/10.5555/789083.1022826
Wang CReddy SPomeranz ILin XRajski JPileggi LKuehlmann A(2002)Conflict driven techniques for improving deterministic test pattern generationProceedings of the 2002 IEEE/ACM international conference on Computer-aided design10.1145/774572.774585(87-93)Online publication date: 10-Nov-2002
https://dl.acm.org/doi/10.1145/774572.774585
Abramovici MYu XRudnick EAckland B(2002)Low-cost sequential ATPG with clock-control DFTProceedings of the 39th annual Design Automation Conference10.1145/513918.513983(243-248)Online publication date: 10-Jun-2002
https://dl.acm.org/doi/10.1145/513918.513983
Hamzaoglu IPatel JSentovich E(2000)Deterministic test pattern generation techniques for sequential circuitsProceedings of the 2000 IEEE/ACM international conference on Computer-aided design10.5555/602902.603023(538-543)Online publication date: 5-Nov-2000
https://dl.acm.org/doi/10.5555/602902.603023
Amyeen MFuchs WPomeranz IBoppana V(1999)Implication and Evaluation Techniques for Proving Fault EquivalenceProceedings of the 1999 17TH IEEE VLSI Test Symposium10.5555/832299.836503Online publication date: 26-Apr-1999
https://dl.acm.org/doi/10.5555/832299.836503
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