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Development of ASIC Chip-Set for High-End Network Processing Application-A Case Study

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Sanjeev PatelAuthors Info & Claims

ASP-DAC '02: Proceedings of the 2002 Asia and South Pacific Design Automation Conference

Page 789

Published: 07 January 2002 Publication History

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Abstract

Choosing the right methodology is a significant step towards successful VLSI designs. Traditional methodologies and tools are no longer adequate to handle large and complex designs. This paper presents a novel design methodology for complex deep-submicron designs, using a case study of the development of a high-end network processing ASIC chip-set. The paper focuses on the synergetic use of the "dual design verification approach", along with static verification methods in achieving defect free silicon. It also discusses the techniques employed for achieving faster and less-iterative timing closure.

References

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{1} Simultaneous Switching Analysis Overview, IBM Application Note, Revision 2, 01/01/99.

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{2} Doug Dreibelbis, Paul Zuchowski, and Patrick Buffet, "Hidden Benefit #4: ASIC's Area-Array I/O Footprint", IBM MicroNews, First Quarter 2001, Vol. 7, No. 1.

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{3} Patrick H. Buffet, et al., "Methodology for I/O Cell Placement and Checking in ASIC Designs Using Area-Array Power Grid", IBM MicroNews, Third Quarter 2000, Vol. 6, No. 3.

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{4} Vivek Chickermane, David Lackey, Dave Litten, and Lori Smudde, "Automated Chip-Level I/O and Test Insertion Using IBM Design-for-Test Synthesis", First Quarter 2000, Vol. 6, No. 2.

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Development of ASIC Chip-Set for High-End Network Processing Application-A Case Study
1. Hardware

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Published In

ASP-DAC '02: Proceedings of the 2002 Asia and South Pacific Design Automation Conference

January 2002

753 pages

ISBN:0769514413

Publisher

IEEE Computer Society

United States

Publication History

Published: 07 January 2002

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ASPDAC/VLSI02

Sponsor:

SIGDA

ASPDAC/VLSI02: ASP-DAC/VLSI Design Conference 2002

January 7 - 11, 2002

Acceptance Rates

Overall Acceptance Rate 466 of 1,454 submissions, 32%

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ASPDAC '25

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30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

Tokyo , Japan

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