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Recent Improvements on the Specification of Transient-Fault Tolerant VHDL Descriptions: A Case-Study for Area Overhead Analysis

Published: 18 September 2000 Publication History

Abstract

We present a new approach to design reliable complex circuits with respect to transient faults in memory elements. These circuits are intended to be used in harmful environments like radiation. During the design flow, this methodology is also used to perform an early-estimation of the obtained reliability level. Usually, this reliability estimation step is performed in the laboratory, by means of radiation facilities (particle accelerators). By doing so, the early-estimated reliability level is used to balance the design process into a trade-off between maximum area overhead due to the insertion of redundancy and the minimum reliability required for a given application. This approach is being automated through the development of a CAD tool (FT-PRO). Finally, we present also a case-study of a simple microprocessor used to analyze the FT-PRO performance in terms of the area overhead required to implement the fault-tolerant circuit.
  1. Recent Improvements on the Specification of Transient-Fault Tolerant VHDL Descriptions: A Case-Study for Area Overhead Analysis

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    cover image ACM Conferences
    SBCCI '00: Proceedings of the 13th symposium on Integrated circuits and systems design
    September 2000
    ISBN:076950843X

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    IEEE Computer Society

    United States

    Publication History

    Published: 18 September 2000

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    Author Tags

    1. CAD tool
    2. FT-PRO tool
    3. SEU
    4. VHDL description specification
    5. area overhead analysis
    6. design methodology
    7. digital integrated circuits
    8. error correction
    9. fault tolerant computing
    10. fault-tolerant circuit
    11. hardware description languages
    12. harmful environments
    13. high level synthesis
    14. integrated circuit design
    15. integrated circuit reliability
    16. memory elements
    17. microprocessor
    18. redundancy
    19. reliability level estimation
    20. reliable complex circuit design
    21. single event upsets
    22. transient-fault tolerant VHDL descriptions
    23. transients

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    Overall Acceptance Rate 133 of 347 submissions, 38%

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