Recent Improvements on the Specification of Transient-Fault Tolerant VHDL Descriptions: A Case-Study for Area Overhead Analysis
Abstract
- Recent Improvements on the Specification of Transient-Fault Tolerant VHDL Descriptions: A Case-Study for Area Overhead Analysis
Recommendations
Transient-fault tolerant VHDL descriptions: a case-study for area overhead analysis
ATS '00: Proceedings of the 9th Asian Test SymposiumWe present a new approach to design reliable complex circuits with respect to transient faults in memory elements. These circuits are intended to be used in harmful environments like radiation. During the design flow this methodology is also used to ...
A Fault-Tolerant Systolic Sorter
A fault-tolerant systolic sorter design is proposed. An algorithm-based fault tolerance is achieved by testing the invariants of a systolic sorter during normal operation. Transient and permanent computation errors can be detected by using error-...
Evaluation of a Soft Error Tolerance Technique Based on Time and/or Space Redundancy
SBCCI '00: Proceedings of the 13th symposium on Integrated circuits and systems designIC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly sensitive to noise, which will result in unacceptable rates of soft-errors. ...
Comments
Please enable JavaScript to view thecomments powered by Disqus.Information & Contributors
Information
Published In
Sponsors
Publisher
IEEE Computer Society
United States
Publication History
Check for updates
Author Tags
- CAD tool
- FT-PRO tool
- SEU
- VHDL description specification
- area overhead analysis
- design methodology
- digital integrated circuits
- error correction
- fault tolerant computing
- fault-tolerant circuit
- hardware description languages
- harmful environments
- high level synthesis
- integrated circuit design
- integrated circuit reliability
- memory elements
- microprocessor
- redundancy
- reliability level estimation
- reliable complex circuit design
- single event upsets
- transient-fault tolerant VHDL descriptions
- transients
Qualifiers
- Article
Acceptance Rates
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 0Total Downloads
- Downloads (Last 12 months)0
- Downloads (Last 6 weeks)0