SBCCI

This paper studies the test pattern generation problem for FPGA implemented combinational circuits. General definitions concerning the specific problem of testing RAM-based FPGAs are first given such as the important concept of manufacturing-oriented ...

The first part of this paper describes the control of CAS-BUS, a P1500 compatible Test Access Mechanism (TAM). Boundary scan features are used to allow controlling of the TAM and the P1500 wrappers. The final architecture characteristics are its ...

This paper describes how technology mapping from VPBDDs is testability preserving. An algorithm for identifying unreachable arcs is presented. Theorems that prove the testability preservation during technology mapping are presented.

Most of the false path-aware timing analysis algorithms were originally developed for circuits made of simple gates, i.e. ANDs/NANDs, ORs/NORs and inverters. However, the availability of efficient CMOS macrocell generators and "library-free" technology ...

This paper describes an architecture of a three input one output bit scalable fuzzy processor. The synthesis is made from a VHDL description. The data path and functional units dimension are defined by a small number of parameters in the highest level ...

This paper presents the design of an early condition resolution circuit. The proposed circuit works in parallel with the arithmetic unit, and calculates the Equal to (EQ), Greater-than (GT), Less-than (LT), Overflow (OV), Underflow (UF), and Carry-out (...

This article proposes a methodology to synthesize extended burst asynchronous state machines operating in a new mode which we called input burst/output burst (I/sub b//O/sub b/), while obeying the bounded gate and wire delay model. In such machines a ...

Data security is an important issue in today's computer networks. This paper presents the improved IDEA chip, which implements a new version of the IDEA cryptographic algorithm. Improved IDEA is oriented towards computer network applications demanding ...

A hypercube or binary n-cube is an interconnection network very suitable for implementing computing elements. In this paper we study the Hamiltonian decomposition, i.e. the partitioning of its edge set into Hamiltonian cycles. It is known that there are ...

Functional decomposition (FD) is a process of breaking a complex and large function into smaller and simpler sub-functions. There exist two strategies in FD (1) Serial and (2) Parallel Decomposition. In this paper we deal with the problem of generating ...

A new approach to a simple disjunctive decomposition of a Boolean function is presented. It is based on using symmetric relations among a function's variables to recognize intrinsic characteristics of the function. The conditions for the existence of a ...

This work presents two approaches for computing the number of functional units in hardware/software codesign context. The proposed hardware/software codesign framework uses Petri net as common formalism for performing quantitative and qualitative ...

A VI-converter is presented with adjustable transconductance suited for low-power operation through transistors biased in weak and moderate inversion. It can process unipolar differential input voltages or perform a correlated double sampling on a ...

This paper presents a redesign procedure for analog circuits based on a scalable model of the MOSFET. A set of very simple expressions allows the calculation of transistor dimensions and bias for a given circuit in a new generation technology, starting ...

A new class AB output stage is presented which extends a family of recently proposed stages based on current mirrors without requiring extra-compensation capacitances. In-depth circuit analysis also shows the significant advantage of such stages for low-...

This paper presents the Trapezoidal Association of Transistors Generator (TATGen) tool, targeted to mixed analog-digital design on the PROCIMS Sea-of-Transistors (SoT) array (1996), in 1.0 /spl mu/m CMOS digital technology (single poly, 2 metal layers). ...

Tight data- and timing constraints are imposed by DSP applications. Also, the target processor architecture or the synthesized circuit template conform resource constraints. Additionally, instead of registers address-limited storage files with fifos or ...

Predicated execution is an efficient mechanism to avoid conditional constructs in application programs. In this paper we describe how an existing method for register binding can be extended to support predicated execution. The method exploits the ...

Allocation is the High Level Synthesis task that reaches a data path definition obeying hardware restriction and optimizing the chip area and performance. Testability is a sequence of procedures that ensures that an ASIC is working correctly. Self-...

This paper briefly describes the new results of the Cave Project. Cave Project is a research initiative aiming to make possible a user-transparent distribution of CAD resources over the World Wide Web. Early results on developing a web based interface ...

This paper presents a www-based macro-cell generator tool integrated in a www-based framework. The Wtropic tool allows user connections through the Internet and it provides a communication layer to execute the physical synthesis tool remotely from any ...

Taking as a starting point for an FPGA program an efficient bit-level systolic algorithm facilitates the design process but does not automatically guarantee the most efficient hardware solution. We use an example of modular exponentiation with ...

Net by net routing is still a very important technique used to make connections in VLSI circuits. The maze routing algorithms used for this purpose correspond to shortest path searches derived from basic BFS or from A*, with many dedicated improvements. ...

This paper describes a novel design method for digital logic circuits based on the resonant-tunneling-heterojunction-bipolar-transistor (RTBT). Besides drift and diffusion, the RTBT uses tunneling as transport mechanism leading to an enhanced I-V ...

System level designs are typically heterogeneous, thus combining different technologies. In order to create executable specifications at such a level, a hardware description language, a programming language, or a combination of both is used. However, ...