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View all- Dees WParmar KGoyal ATsui RRathi BSmith R(1981)A computer-aided VLSI layout systemProceedings of the May 4-7, 1981, national computer conference10.1145/1500412.1500415(11-18)Online publication date: 4-May-1981
This paper describes a design system capable of designing chips in the range of 5K to 7K equivalent three-way NOR gates. A key feature of the system is the ability to design chips with large macros (RAMs and PLAs). This design system is part of IBM's ...
Array multipliers are well suited for VLSI implementation because of the regularity in their iterative structure. However, most VLSI circuits are difficult to test. This correspondence shows that, with appropriate cell design, array multipliers can be ...
Since Japanese R&D efforts began in the late 1960s, advances in LSI circuit design automation have made possible the designof custom logic VLSI circuits with up to 10,000 gates. Automatic placement and routing programs have become essential DA toolsin ...
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