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Auto-delay: A program for automatic calculation of delay in LSI/VLSI chips

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Rathin PutatundaAuthors Info & Claims

DAC '82: Proceedings of the 19th Design Automation Conference

Pages 616 - 621

Published: 01 January 1982 Publication History

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Abstract

This paper describes a program for automatically computing the delay through LSI/VLSI chips which have been laid out using automatic layout programs. A unique algoristhm for synthesizing RC networks from artwork data, which significantly reduces execution time and computer storage, is included. A novel and simple method for determining the delay through logic gates due to arbitrary RC network load at the output is also presented and discussed.

References

[1]

Mead and Conway, Introduction to VLSI, Addison-Wesley Series, 1980.

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[2]

E. N. Protonotarios and O. Wing, "Theory of Non-Uniform RC Lines, Part II: Analytic Properties in the Time Domain," IEEE Transactions of Circuit Theory, Vol. 14, No. 1, pp. 13-20; March 1967.

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[3]

K. Singhal and J. Vlach, "Calculation of Time Responses of Non-Uniform RC-Distributed Active Networks," Digest of Technical Papers, London 1971 IEEE International Symposium on Electrical Network Theory, London, England, pp. 75-76; September 6-10, 1971.

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[4]

P. Penfield and J. Rubinstein, "Signal Delay in RC Tree Networks," 18th Design Automation Conference, pp. 613-617, 1981.

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[5]

R. Noto et al., "Automated Design Procedures for VLSI", Research and Development Technical Report to U.S. Army Electronics Research and Development Command, Fort Monmouth, NJ, March 1981.

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Cited By

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Ratzlaff CGopal NPillage LNewton A(1991)RICEProceedings of the 28th ACM/IEEE Design Automation Conference10.1145/127601.127732(555-560)Online publication date: 1-Jun-1991
https://dl.acm.org/doi/10.1145/127601.127732
Benkoski JStrojwas ANewton A(1991)The role of timing verification in layout synthesisProceedings of the 28th ACM/IEEE Design Automation Conference10.1145/127601.122895(612-619)Online publication date: 1-Jun-1991
https://dl.acm.org/doi/10.1145/127601.122895
Pillage LHuang XRohrer RThomas D(1989)AWEsim: asymptotic waveform evaluation for timing analysisProceedings of the 26th ACM/IEEE Design Automation Conference10.1145/74382.74493(634-637)Online publication date: 1-Jun-1989
https://dl.acm.org/doi/10.1145/74382.74493
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Index Terms

Auto-delay: A program for automatic calculation of delay in LSI/VLSI chips
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Partitioning and floorplanning
  2. Very large scale integration design
2. Mathematics of computing
  1. Mathematical analysis
    1. Integral equations

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DAC '82: Proceedings of the 19th Design Automation Conference

January 1982

919 pages

ISBN:0897910206

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IEEE Press

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Published: 01 January 1982

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Ratzlaff CGopal NPillage LNewton A(1991)RICEProceedings of the 28th ACM/IEEE Design Automation Conference10.1145/127601.127732(555-560)Online publication date: 1-Jun-1991
https://dl.acm.org/doi/10.1145/127601.127732
Benkoski JStrojwas ANewton A(1991)The role of timing verification in layout synthesisProceedings of the 28th ACM/IEEE Design Automation Conference10.1145/127601.122895(612-619)Online publication date: 1-Jun-1991
https://dl.acm.org/doi/10.1145/127601.122895
Pillage LHuang XRohrer RThomas D(1989)AWEsim: asymptotic waveform evaluation for timing analysisProceedings of the 26th ACM/IEEE Design Automation Conference10.1145/74382.74493(634-637)Online publication date: 1-Jun-1989
https://dl.acm.org/doi/10.1145/74382.74493
Tamura EOgawa KNakano TRadke COfek HShaklee DLosleben PNash JPistilli PLambert PPreas BLerman H(1983)Path delay analysis for hierarchical building block layout systemProceedings of the 20th Design Automation Conference10.5555/800032.800699(403-410)Online publication date: 27-Jun-1983
https://dl.acm.org/doi/10.5555/800032.800699
Bastian JEllement MFowler PHuang CMcNamee LRadke COfek HShaklee DLosleben PNash JPistilli PLambert PPreas BLerman H(1983)Symbolic Parasitic Extractor for Circuit Simulation (SPECS)Proceedings of the 20th Design Automation Conference10.5555/800032.800687(346-352)Online publication date: 27-Jun-1983
https://dl.acm.org/doi/10.5555/800032.800687

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Constant delay logic style

Switch-level delay test

Delay Fault Testability on Two-Rail Logic Circuits

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