VMP is an experimental multiprocessor that follows the familiar basic design of multiple processors, each with a cache, connected by a shared bus to global memory. Each processor has a synchronous, virtually addressed, single master connection to its cache, providing very high memory bandwidth. An unusually large cache page size and fast sequential memory copy hardware make it feasible for cache misses to be handled in software, analogously to the handling of virtual memory page faults. Hardware support for cache consistency is limited to a simple state machine that monitors the bus and interrupts the processor when a cache consistency action is required. In this paper, we show how the VMP design provides the high memory bandwidth required by modern high-performance processors with a minimum of hardware complexity and cost. We also describe simple solutions to the consistency problems associated with virtually addressed caches. Simulation results indicate that the design achieves good performance providing data contention is not excessive.
Cited By
- Kanellopoulos K, Bera R, Stojiljkovic K, Bostanci F, Firtina C, Ausavarungnirun R, Kumar R, Hajinazar N, Sadrosadati M, Vijaykumar N and Mutlu O Utopia: Fast and Efficient Address Translation via Hybrid Restrictive & Flexible Virtual-to-Physical Address Mappings Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, (1196-1212)
- Kanellopoulos K, Nam H, Bostanci N, Bera R, Sadrosadati M, Kumar R, Bartolini D and Mutlu O Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, (1178-1195)
- Kanakia H and Cheriton D (2019). The VMP network adapter board (NAB): high-performance network communication for multiprocessors, ACM SIGCOMM Computer Communication Review, 18:4, (175-187), Online publication date: 1-Aug-1988.
- Kanakia H and Cheriton D The VMP network adapter board (NAB): high-performance network communication for multiprocessors Symposium proceedings on Communications architectures and protocols, (175-187)
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