Test Pattern Decompression Using a Scan Chain

In the paper we propose a method of test pattern compression, which can be used for reducing the memory requirements for storing test patterns. The patterns are decompressed during testing in the scan chain. The test-per-clock testing scheme consists of a scan chain, auxiliary outputs for capturing the signals on the internal CUT outputs and a CUT test response compactor. The test-per-scan testing scheme can be used without auxiliary outputs and output compacting scheme. The algorithm of finding the compressed scan chain sequence reorders and overlaps the patterns previously generated with the help of an ATPG. These test patterns are generated in such a way that they contain maximum number of don't care bits. The scan chain sequence can be used for exercising all considered faults from the fault list of the tested circuit. Several experiments were done with ISCAS 85 and 89 benchmark circuits. Comparing with other methods the proposed method substantially reduces the number of stored bits, test application time and necessary hardware overhead.