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Efficient Scheduling of DSP Code on Processors with Distributed Register Files

Authors:

Bart Mesman,

Carlos A. Alba Pinto,

Koen Van EijkAuthors Info & Claims

ISSS '99: Proceedings of the 12th international symposium on System synthesis

Page 100

Published: 01 November 1999 Publication History

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Abstract

Code generation methods for digital signal processors are increasingly hampered by the combination of tight timing constraints imposed by the algorithms and the limited capacity of the available register files. Traditional methods that schedule spill code to satisfy storage capacity have difficulty satisfying the timing constraints. The method presented in this paper analyses the combination of limited register file capacity, resource- and timing constraints during scheduling. Value lifetimes are serialized until all capacity constraints are guaranteed to be satisfied after scheduling. Experiments in the FACTS environment show that we efficiently obtain high quality instruction schedules for inner-most loops of DSP algorithms.

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Cited By

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Wen MWu NGuan MZhang CKyung CChoi KHa S(2008)Load schedulingProceedings of the 2008 Asia and South Pacific Design Automation Conference10.5555/1356802.1356888(340-345)Online publication date: 21-Jan-2008
https://dl.acm.org/doi/10.5555/1356802.1356888
Zhao QBasten TMesman Bvan Eijk CJess JHermida RAboulhamid E(2001)Static resource models of instruction setsProceedings of the 14th international symposium on Systems synthesis10.1145/500001.500038(159-164)Online publication date: 30-Sep-2001
https://dl.acm.org/doi/10.1145/500001.500038
Bekooij MJess Jvan Meerbergen JHermida RAboulhamid E(2001)Phase coupled operation assignment for VLIW processors with distributed register filesProceedings of the 14th international symposium on Systems synthesis10.1145/500001.500029(118-123)Online publication date: 30-Sep-2001
https://dl.acm.org/doi/10.1145/500001.500029
Show More Cited By

Efficient Scheduling of DSP Code on Processors with Distributed Register Files
1. Theory of computation
  1. Design and analysis of algorithms
    1. Approximation algorithms analysis
  2. Theory and algorithms for application domains
    1. Machine learning theory
      1. Reinforcement learning

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Information & Contributors

Information

Published In

ISSS '99: Proceedings of the 12th international symposium on System synthesis

November 1999

133 pages

ISBN:076950356X

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 November 1999

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ISSS99

Sponsor:

SIGDA

ISSS99: 12th International Symposium on System Synthesis

November 1 - 4, 1999

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Overall Acceptance Rate 38 of 71 submissions, 54%

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Cited By

View all

Wen MWu NGuan MZhang CKyung CChoi KHa S(2008)Load schedulingProceedings of the 2008 Asia and South Pacific Design Automation Conference10.5555/1356802.1356888(340-345)Online publication date: 21-Jan-2008
https://dl.acm.org/doi/10.5555/1356802.1356888
Zhao QBasten TMesman Bvan Eijk CJess JHermida RAboulhamid E(2001)Static resource models of instruction setsProceedings of the 14th international symposium on Systems synthesis10.1145/500001.500038(159-164)Online publication date: 30-Sep-2001
https://dl.acm.org/doi/10.1145/500001.500038
Bekooij MJess Jvan Meerbergen JHermida RAboulhamid E(2001)Phase coupled operation assignment for VLIW processors with distributed register filesProceedings of the 14th international symposium on Systems synthesis10.1145/500001.500029(118-123)Online publication date: 30-Sep-2001
https://dl.acm.org/doi/10.1145/500001.500029
Leupers RKurdahi FHermida R(2000)Code generation for embedded processorsProceedings of the 13th international symposium on System synthesis10.5555/501790.501827(173-178)Online publication date: 20-Sep-2000
https://dl.acm.org/doi/10.5555/501790.501827
Busá Nvan der Werf ABekooij MKurdahi FHermida R(2000)Scheduling coarse-grain operations for VLIW processorsProceedings of the 13th international symposium on System synthesis10.5555/501790.501802(47-53)Online publication date: 20-Sep-2000
https://dl.acm.org/doi/10.5555/501790.501802

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Enabling compiler flow for embedded VLIW DSP processors with distributed register files

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