Performance analysis of ATM switches with multistage packet switching interconnection networks

A mathematical method for analysis of ATM switches based on multistage packet switching interconnection networks with finite buffering capacity at the output of switching elements is presented. The proposed mathematical method is general in that it analyzed ATM switches under uniform and nonuniform traffic with blocking. The existing methods for analysis of ATM switches with buffered interconnection networks, have assumed either single or infinite buffers at each input (or output) port of a switch, as well as uniform traffic pattern of the networks. Firstly in the paper a general model of a synchronous buffered switching element, using output buffering, under the assumption of finite buffer size for a very general class of traffic patterns, is presented. It is assumed that the subsequent stages of the network are nearly independent and a model is extended for an entire network under this assumption. Analytical results obtained with the proposed model are then compared with each other and it is shown that the proposed mathematical method is more general than the known models.