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Using MTBDDs for Discrete Timed Symbolic Model Checking

Published: 17 March 1997 Publication History

Abstract

The verification of timing properties is an important task in the validation process of embedded and real time systems. Temporal logic model checking is one of the most successful techniques as it allows the complete automation of the verification. In this paper, we present a new approach to symbolic QCTL (Quantitative CTL) model checking. In contrast to previous approaches we use an intuitive QCTL semantics, provide an efficient model representation and the new algorithms require less iteration steps compared to translating the QCTL problem into CTL and using standard CTL model checking techniques. The new model checking algorithm is based on a MTBDD representation. Some experimental results show the efficiency of the new approach.

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Cited By

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  • (1999)Computing timed transition relations for sequential cycle-based simulationProceedings of the conference on Design, automation and test in Europe10.1145/307418.307427(4-es)Online publication date: 1-Jan-1999

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Published In

cover image ACM Conferences
EDTC '97: Proceedings of the 1997 European conference on Design and Test
March 1997
596 pages
ISBN:0818677864

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IEEE Computer Society

United States

Publication History

Published: 17 March 1997

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Author Tags

  1. MTBDD
  2. QCTL semantics
  3. algorithm
  4. automation
  5. discrete timed symbolic model checking
  6. embedded system
  7. formal verification
  8. iteration
  9. multi-valued binary decision diagram
  10. quantitative computation tree logic
  11. real time system
  12. temporal logic
  13. timing properties
  14. validation
  15. verification

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  • (1999)Computing timed transition relations for sequential cycle-based simulationProceedings of the conference on Design, automation and test in Europe10.1145/307418.307427(4-es)Online publication date: 1-Jan-1999

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