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The Road Ahead: The significance of packaging

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Andrew KahngAuthors Info & Claims

IEEE Design & Test, Volume 19, Issue 6

Pages 104 - 105

Published: 01 November 2002 Publication History

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Li SLim KFaraboschi PChang JRanganathan PJouppi NGaluzzi CCarro LMoshovos APrvulovic M(2011)System-level integrated server architectures for scale-out datacentersProceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/2155620.2155651(260-271)Online publication date: 3-Dec-2011
https://dl.acm.org/doi/10.1145/2155620.2155651
Bahukudumbi SOzev SChakrabarty KIyengar V(2009)Wafer-level defect screening for "big-D/small-A" mixed-signal SoCsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200607517:4(587-592)Online publication date: 1-Apr-2009
https://dl.acm.org/doi/10.1109/TVLSI.2008.2006075
Bahukudumbi SChakrabarty K(2009)Test-length and TAM optimization for wafer-level reduced pin-count testing of core-based SoCsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2008.200915028:1(111-120)Online publication date: 1-Jan-2009
https://dl.acm.org/doi/10.1109/TCAD.2008.2009150
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The Road Ahead: The significance of packaging
1. General and reference
2. Social and professional topics
  1. Professional topics
    1. Computing industry

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Published In

IEEE Design & Test Volume 19, Issue 6

November 2002

120 pages

ISSN:0740-7475

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IEEE Computer Society Press

Washington, DC, United States

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Published: 01 November 2002

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Li SLim KFaraboschi PChang JRanganathan PJouppi NGaluzzi CCarro LMoshovos APrvulovic M(2011)System-level integrated server architectures for scale-out datacentersProceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/2155620.2155651(260-271)Online publication date: 3-Dec-2011
https://dl.acm.org/doi/10.1145/2155620.2155651
Bahukudumbi SOzev SChakrabarty KIyengar V(2009)Wafer-level defect screening for "big-D/small-A" mixed-signal SoCsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200607517:4(587-592)Online publication date: 1-Apr-2009
https://dl.acm.org/doi/10.1109/TVLSI.2008.2006075
Bahukudumbi SChakrabarty K(2009)Test-length and TAM optimization for wafer-level reduced pin-count testing of core-based SoCsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2008.200915028:1(111-120)Online publication date: 1-Jan-2009
https://dl.acm.org/doi/10.1109/TCAD.2008.2009150
Bahukudumbi SOzev SChakrabarty KIyengar V(2007)AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCsProceedings of the 2007 Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2007.358091(823-828)Online publication date: 23-Jan-2007
https://dl.acm.org/doi/10.1109/ASPDAC.2007.358091

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