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IC power distribution challenges

Published: 04 November 2001 Publication History

Abstract

With each technology generation, delivering a timevarying current with reduced nominal supply voltage variation is becoming more difficult due to increasing current and power requirements. The power delivery network design becomes much more complex and requires accurate analysis and optimizations at all levels of abstraction in order to meet the specifications. In this paper, we describe techniques for estimation of the supply voltage variations that can be used in the design of the power delivery network. We also describe the decoupling capacitor hierarchy that provides a low impedance to the increasing high-frequency current demand and limits the supply voltage variations. Techniques for high-level power estimation that can be used for performance vs. power trade-offs to reduce the current and power requirements of the circuit are also presented.

Supplementary Material

ZIP File (a643-bobba.zip)
Presentations from the 2001 ICCAD conference: Interconnect extraction, power distribution, and hierarchical design

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Published In

cover image ACM Conferences
ICCAD '01: Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
November 2001
656 pages
ISBN:0780372492
  • Conference Chair:
  • Rolf Ernst

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IEEE Press

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Published: 04 November 2001

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ICCAD01
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ICCAD01: International Conference on Computer Aided Design
November 4 - 8, 2001
California, San Jose

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

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  • (2007)Clock distribution techniques for Low-EMI designProceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation10.5555/2391795.2391821(201-210)Online publication date: 3-Sep-2007
  • (2006)Fast decap allocation based on algebraic multigridProceedings of the 2006 IEEE/ACM international conference on Computer-aided design10.1145/1233501.1233525(107-111)Online publication date: 5-Nov-2006
  • (2006)Localized On-Chip Power Delivery Network Optimization via Sequence of Linear ProgrammingProceedings of the 7th International Symposium on Quality Electronic Design10.1109/ISQED.2006.81(272-277)Online publication date: 27-Mar-2006
  • (2006)Spectral analysis of the on-chip waveforms to generate guidelines for EMC-aware designProceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation10.1007/11847083_52(532-542)Online publication date: 13-Sep-2006
  • (2005)Partitioning-based approach to fast on-chip decap budgeting and minimizationProceedings of the 42nd annual Design Automation Conference10.1145/1065579.1065627(170-175)Online publication date: 13-Jun-2005
  • (2005)Fast Decap Allocation Algorithm For Robust On-Chip Power DeliveryProceedings of the 6th International Symposium on Quality of Electronic Design10.1109/ISQED.2005.57(542-547)Online publication date: 21-Mar-2005
  • (2005)Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect ArchitectureProceedings of the 6th International Symposium on Quality of Electronic Design10.1109/ISQED.2005.29(153-158)Online publication date: 21-Mar-2005
  • (2005)Power supply selective mapping for accurate timing analysisProceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation10.1007/11556930_28(267-276)Online publication date: 21-Sep-2005
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