Article

Latency Insensitive Protocols

Authors:

Luca P. Carloni,

Kenneth L. McMillan,

Alberto L. Sangiovanni-VincentelliAuthors Info & Claims

CAV '99: Proceedings of the 11th International Conference on Computer Aided Verification

Pages 123 - 133

Published: 06 July 1999 Publication History

Abstract

The theory of latency insensitive design is presented as the foundation of a new correct by construction methodology to design very large digital systems by assembling blocks of Intellectual Properties. Latency insensitive designs are synchronous distributed systems and are realized by assembling functional modules exchanging data on communication channels according to an appropriate protocol. The goal of the protocol is to guarantee that latency insensitive designs composed of functionally correct modules, behave correctly independently of the wire delays. A latency-insensitive protocol is presented that makes use of relay stations buffering signals propagating along long wires. To guarantee correct behavior of the overall system, modules must satisfy weak conditions. The weakness of the conditions makes our method widely applicable.

References

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L. P. Carloni, K. L. McMillan, and Alberto L. Sangiovanni-Vincentelli. Latency-Insensitive Protocols. Technical Report UCB/ERL M99/11, Electronics Research Lab, University of California, Berkeley, CA 94720, February 1999.

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Published In

CAV '99: Proceedings of the 11th International Conference on Computer Aided Verification

July 1999

483 pages

ISBN:3540662022

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Springer-Verlag

Berlin, Heidelberg

Publication History

Published: 06 July 1999

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Ben Khadra MBai YSchneider K(2014)High level modeling of elastic circuits in SystemCProceedings of the Symposium on Theory of Modeling & Simulation - DEVS Integrative10.5555/2665008.2665032(1-8)Online publication date: 13-Apr-2014
https://dl.acm.org/doi/10.5555/2665008.2665032
(2013)Equivalence checking for synchronous elastic circuitsProceedings of the Eleventh ACM/IEEE International Conference on Formal Methods and Models for Codesign10.5555/3041405.3041490(109-118)Online publication date: 1-Oct-2013
https://dl.acm.org/doi/10.5555/3041405.3041490
(2010)A design flow based on modular refinementProceedings of the Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign10.1109/MEMCOD.2010.5558626(11-20)Online publication date: 1-Jul-2010
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Vijayaraghavan MArvind A(2009)Bounded dataflow networks and latency-insensitive circuitsProceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign10.5555/1715759.1715781(171-180)Online publication date: 13-Jul-2009
https://dl.acm.org/doi/10.5555/1715759.1715781
Cong JLiu ALiu BRosenstiel WWakabayashi K(2009)A variation-tolerant scheduler for better than worst-case behavioral synthesisProceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis10.1145/1629435.1629467(221-228)Online publication date: 11-Oct-2009
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Suhaib SMathaikutty DShukla S(2008)A trace-based framework for verifiable GALS composition of IPsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200086916:9(1176-1186)Online publication date: 1-Sep-2008
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Lin CWang JZhou H(2006)Clustering for processing rate optimizationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2006.88639914:11(1264-1275)Online publication date: 1-Nov-2006
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Suhaib SMathaikutty DBerner DShukla S(2006)Validating Families of Latency Insensitive ProtocolsIEEE Transactions on Computers10.1109/TC.2006.18855:11(1391-1401)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TC.2006.188
(2006)Latency-insensitive design and central repetitive schedulingProceedings of the Fourth ACM/IEEE International Conference on Formal Methods and Models for Co-Design10.1109/MEMCOD.2006.1695923(175-183)Online publication date: 1-Jan-2006
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Lin CWang JZhou H(2005)Clustering for processing rate optimizationProceedings of the 2005 IEEE/ACM International conference on Computer-aided design10.5555/1129601.1129629(189-195)Online publication date: 31-May-2005
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Cited By

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Theory of latency-insensitive design

From multi-clocked synchronous processes to latency-insensitive modules

Context-insensitive alias analysis reconsidered

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