Nothing Special   »   [go: up one dir, main page]

skip to main content
10.5555/647042.713812guideproceedingsArticle/Chapter ViewAbstractPublication PagespactConference Proceedingsconference-collections
Article

An Evaluation of Optimized Threaded Code Generation

Published: 24 August 1994 Publication History

Abstract

No abstract available.

References

[1]
B. J. Smith. Architecture and Applications of the HEP Multiprocessor Computer System. SPIE (Real Time Signal Processing, 298:241--248, 1981.
[2]
R. Alverson, D. Callahan, D. Cummings, B. Koblenz, A. Portfield, and B. Smith. The Tera computer system. In Proc. Int. Conf. on Supercomputing, pages 1--6. ACM Press, June 1990.
[3]
G. M. Papadopoulos and D. E. Culler. Monsoon: an explicit token-store architecture. In Int. Ann. Symp. on Computer Architecture, June 1990.
[4]
R. S. Nikhil, G. M. Papadopoulos, and Arvind. *T: A multithreaded massively parallel architecture. In Int. Ann. Symp. on Computer Architecture, 1992.
[5]
S. Sakai, Y. Yamaguchi, K. Hiraki, Y. Kodama, and T. Yuba. An architecture of a data-flow single chip processor. In Int. Ann. Symp. on Computer Architecture, pages 46--53, May 1989.
[6]
R. A. Iannucci. Toward A Dataflow/Von Neumann Hybrid Architecture. In Int. Ann. Symp. on Computer Architecture, pages 131--140, 1988.
[7]
K. E. Schauser, D. E. Culler, and T. von Eicken. Compiler-controlled multithreading for lenient parallel languages. In J. Hughes, editor, Conf. on Functional Programming Languages and Computer Architecture, 1991.
[8]
J. E. Hoch, D. M. Davenport, V. G. Grafe, and K. M. Steele. Compile time partitioning of a non-strict language into sequential threads. Technical report, Sandia National Laboratory, 1992.
[9]
K. R. Traub. Multithread code generation for dataflow architetures from non-strict programs. In J. Hughes, editor, Conf. on Functional Programming Languages and Computer Architecture, 1991.
[10]
L. Roh, W. A. Najjar, and A. P. W. Böhm. Generation and quantitative evaluation of dataflow clusters. In Conf. on Functional Programming Languages and Computer Architecture, Copenhagen, Denmark, June 1993.
[11]
V. Sarkar. Partitioning and scheduling parallel programs for execution on multiprocessors. Technical Report CSL-TR-87-328, Stanford University, Computer Systems Laboratory, April 1987.
[12]
L. Bic, M. Nagel, and J. Roy. Automatic data/program partitioning using the single assignment principle. In Proc. Supercomputing '89, Reno, Nevada, 1989.
[13]
M. Girkar and C. D. Polychronopolous. Automatic extraction of functional parallelism from ordinary programs. IEEE Transactions on Parallel and Distributed Systems, 3(2):166--177, March 1992.
[14]
W. A. Najjar, L. Roh, and A. P. W. Böhm. The initial performance of a bottom-up clustering algorithm for dataflow graphs. In Proc. of the IFIP WG 10.3 Conf. on Architecture and Compilation Techniques for Medium and Fine Grain Parallelism, Orlando, FL, January 1993.
[15]
A. P. W. Böhm, W. A. Najjar, B. Shankar, and L. Roh. An evaluation of bottom-up and top-down thread generation techniques. In 26<sup>th</sup> ACM/IEEE International Symposium on Micrtoarchitecture (MICRO-26), 1993.
[16]
W. A. Najjar, W. M. Miller, and A. P. W. Böhm. An analysis of loop latency in dataflow execution. In Int. Ann. Symp. on Computer Architecture, Gold Coast, Australia, May 1992.
[17]
D. E. Culler and G. M. Papadopoulos. The explicit token store. Journal of Parallel and Distributed Computing, 10(4), 1990.

Cited By

View all
  • (2001)The Sisal projectCompiler optimizations for scalable parallel systems10.5555/380466.380468(45-72)Online publication date: 1-Jun-2001
  • (2000)Automatic compiler techniques for thread coarsening for multithreaded architecturesProceedings of the 14th international conference on Supercomputing10.1145/335231.335261(306-315)Online publication date: 8-May-2000
  • (1997)The Sisal Model of Functional Programming and its ImplementationProceedings of the 2nd AIZU International Symposium on Parallel Algorithms / Architecture Synthesis10.5555/523978.826095Online publication date: 17-Mar-1997
  • Show More Cited By

Recommendations

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image Guide Proceedings
PACT '94: Proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques
August 1994
342 pages

Publisher

North-Holland Publishing Co.

Netherlands

Publication History

Published: 24 August 1994

Qualifiers

  • Article

Acceptance Rates

Overall Acceptance Rate 121 of 471 submissions, 26%

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)0
  • Downloads (Last 6 weeks)0
Reflects downloads up to 13 Nov 2024

Other Metrics

Citations

Cited By

View all
  • (2001)The Sisal projectCompiler optimizations for scalable parallel systems10.5555/380466.380468(45-72)Online publication date: 1-Jun-2001
  • (2000)Automatic compiler techniques for thread coarsening for multithreaded architecturesProceedings of the 14th international conference on Supercomputing10.1145/335231.335261(306-315)Online publication date: 8-May-2000
  • (1997)The Sisal Model of Functional Programming and its ImplementationProceedings of the 2nd AIZU International Symposium on Parallel Algorithms / Architecture Synthesis10.5555/523978.826095Online publication date: 17-Mar-1997
  • (1997)Thread partitioning and scheduling based on cost modelProceedings of the ninth annual ACM symposium on Parallel algorithms and architectures10.1145/258492.258519(272-281)Online publication date: 1-Jun-1997
  • (1995)Design of storage hierarchy in multithreaded architecturesProceedings of the 28th annual international symposium on Microarchitecture10.5555/225160.225203(271-278)Online publication date: 1-Dec-1995
  • (1995)Control of loop parallelism in multithreaded codeProceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques10.5555/224659.224707(131-139)Online publication date: 27-Jun-1995
  • (1995)Analysis of communications and overhead reduction in multithreaded executionProceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques10.5555/224659.224704(122-130)Online publication date: 27-Jun-1995

View Options

View options

Get Access

Login options

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media