Microarchitectural synthesis of gracefully degradable, dynamically reconfigurable ASICs

We propose a novel graceful degradation scheme, L/U reconfiguration, which can tolerate a single permanent fault in each hardware class of ASIC data paths. In the proposed scheme, dynamic hardware rebinding and operation rescheduling are performed by a ...

We present two novel reconfiguration schemes, L/U reconfiguration and its generalization, band reconfiguration, to achieve graceful degradation for general microarchitecture datapaths. Upon detection of a datapath fault, hardware and algorithmic ...

In an increasing number of applications, reliability is essential. On-line resiliency when confronted with permanent faults is a difficult and important aspect of providing reliability. Particularly vexing is the problem of fault identification. Current ...