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Theory and Design Switching CircJune 1985
Abstract
No abstract available.
Cited By
- Gabrijel I and Dobnikar A (2003). On-line identification and reconstruction of finite automata with generalized recurrent neural networks, Neural Networks, 16:1, (101-120), Online publication date: 1-Jan-2003.
- Fujiwara H (2000). A New Class of Sequential Circuits with Combinational Test Generation Complexity, IEEE Transactions on Computers, 49:9, (895-905), Online publication date: 1-Sep-2000.
- Das D, Bhattacharya U and Bhattacharya B (2000). Isomorph-Redundancy in Sequential Circuits, IEEE Transactions on Computers, 49:9, (992-997), Online publication date: 1-Sep-2000.
- Iyengar V, Trevillyan L and Bose P Representative Traces for Processor Models with Infinite Cache Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
- Devadas S, Keutzer K, Malik S and Wang A (1994). Verification of asynchronous interface circuits with bounded wire delays, Journal of VLSI Signal Processing Systems, 7:1-2, (161-182), Online publication date: 1-Feb-1994.
- Kantabutra V and Andreou A (1994). A State Assignment Approach to Asynchronous CMOS Circuit Design, IEEE Transactions on Computers, 43:4, (460-469), Online publication date: 1-Apr-1994.
- Chu T, Mani N and Leung C An efficient critical race-free state assignment technique for asynchronous finite state machines Proceedings of the 30th international Design Automation Conference, (2-6)
- Devadas S, Keutzer K, Malik S and Wang A Verification of asynchronous interface circuits with bounded wire delays Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, (188-195)
- Fang K and Wojcik A (2019). Modular Decomposition of Combinatorial Multiple-Values Circuits, IEEE Transactions on Computers, 37:10, (1293-1301), Online publication date: 1-Oct-1988.
- Pradhan D (1983). Sequential Network Design Using Extra Inputs for Fault Detection, IEEE Transactions on Computers, 32:3, (319-323), Online publication date: 1-Mar-1983.
- Lin G and Menon P (1983). Totally Preset Checking Experiments for Sequential Machines, IEEE Transactions on Computers, 32:2, (101-108), Online publication date: 1-Feb-1983.
- Abramovici M, Levendel Y and Menon P (2019). A logic simulation machine, ACM SIGARCH Computer Architecture News, 10:3, (148-157), Online publication date: 1-Apr-1982.
- Abramovici M, Levendel Y and Menon P A logic simulation machine Proceedings of the 9th annual symposium on Computer Architecture, (148-157)
- Abramovici M, Levendel Y and Menon P A logic simulation machine Proceedings of the 19th Design Automation Conference, (65-73)
- Leinwand S Logical correctness by construction Proceedings of the 19th Design Automation Conference, (825-831)
- Dervisoglu B and Sholl H (1980). Theory and Design of Mixed-Mode Sequential Machines, IEEE Transactions on Computers, 29:7, (639-648), Online publication date: 1-Jul-1980.
- Leinwand S and Lamdan T Algebraic analysis of nondeterministic behavior Proceedings of the 17th Design Automation Conference, (483-493)
- Leinwand S and Lamdan T Design verification based on functional abstraction Proceedings of the 16th Design Automation Conference, (353-359)
- Thompson R and Gray F (1978). Universal Modular Trees, IEEE Transactions on Computers, 27:1, (53-63), Online publication date: 1-Jan-1978.
- Yang T and Wojcik A Parallel and serial decompositions of multi-valued sequential machines Proceedings of the eighth international symposium on Multiple-valued logic, (179-186)
- Kuhl J and Reddy S (1978). A Multicode Single Transition-Time State Assignment for Asynchronous Sequential Machines, IEEE Transactions on Computers, 27:10, (927-934), Online publication date: 1-Oct-1978.
- Kartashev S and Kartashev S (1978). On Modular Networks Satisfying the Shift-Register Rule, IEEE Transactions on Computers, 27:12, (1153-1176), Online publication date: 1-Dec-1978.
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