Power-conscious test synthesis and scheduling

Previous research has outlined that power dissipatedduring test application is substantially higher than duringfunctional operation, which leads to loss of yield and decreases reliability. This paper shows for the first time howpower is minimized in ...

In the paper, a methodology of power conscious RTL test scheduling is described. The methodology is based on the fact that circuit under analysis (CUA) is partitioned into testable blocks (TB), the information about the partitioning is the input ...

Both average power and peak power specifications of a circuit pose serious problems for the prevalent test methods like scan and built-in self-test. This tutorial discusses the problems and solutions for minimizing power dissipation in these test ...