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Timing analysis with known false sub graphs

Authors:

Krishna P. Belkhale,

Alexander J. SuessAuthors Info & Claims

ICCAD '95: Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Pages 736 - 740

Published: 01 December 1995 Publication History

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References

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Cited By

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Cheng LChen DWong MHutton MGovig JGielen G(2007)Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domainsProceedings of the 2007 IEEE/ACM international conference on Computer-aided design10.5555/1326073.1326149(370-375)Online publication date: 5-Nov-2007
https://dl.acm.org/doi/10.5555/1326073.1326149
Gandikota RChopra KBlaauw DSylvester DBecer MLevitan S(2007)Top-k aggressors sets in delay noise analysisProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278523(174-179)Online publication date: 4-Jun-2007
https://dl.acm.org/doi/10.1145/1278480.1278523
Zhou SYao BChen HZhu YCheng CHutton MHirose F(2006)Efficient static timing analysis using a unified framework for false paths and multi-cycle pathsProceedings of the 2006 Asia and South Pacific Design Automation Conference10.1145/1118299.1118317(73-78)Online publication date: 24-Jan-2006
https://dl.acm.org/doi/10.1145/1118299.1118317
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Timing analysis with known false sub graphs

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Timing Analysis with Known False Sub Graphs
ICCAD '95: Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

In this paper, we formulate the problem of timing analysis with known false sub graphs. This problem is important when we want the timing analysis system to take into account false path information that is supplied either by the user or by another ...
Efficient Timing Analysis With Known False Paths Using Biclique Covering

We improve the efficiency of static timing analysis when false paths are considered. The efficiency of timing analysis is critical for the performance driven optimization program because timing analysis is invoked heavily in the inner loop. However, ...
Removing user specified false paths from timing graphs
DAC '00: Proceedings of the 37th Annual Design Automation Conference

We present a new method for removing user-specified false subgraphs from timing analysis and circuit optimization. Given a timing graph and a list of specified false paths, false subpaths, or false subgraphs, we generate a new timing graph in which all ...

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Published In

ICCAD '95: Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

December 1995

748 pages

ISBN:0818672137

Chairman:
Richard Rudell
Synopsys, Inc., Mountain View, CA

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 December 1995

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ICCAD '95

Sponsor:

SIGDA
IEEE-CS

ICCAD '95: International Conference on Computer Aided Design

November 5 - 9, 1995

California, San Jose, USA

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

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Cheng LChen DWong MHutton MGovig JGielen G(2007)Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domainsProceedings of the 2007 IEEE/ACM international conference on Computer-aided design10.5555/1326073.1326149(370-375)Online publication date: 5-Nov-2007
https://dl.acm.org/doi/10.5555/1326073.1326149
Gandikota RChopra KBlaauw DSylvester DBecer MLevitan S(2007)Top-k aggressors sets in delay noise analysisProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278523(174-179)Online publication date: 4-Jun-2007
https://dl.acm.org/doi/10.1145/1278480.1278523
Zhou SYao BChen HZhu YCheng CHutton MHirose F(2006)Efficient static timing analysis using a unified framework for false paths and multi-cycle pathsProceedings of the 2006 Asia and South Pacific Design Automation Conference10.1145/1118299.1118317(73-78)Online publication date: 24-Jan-2006
https://dl.acm.org/doi/10.1145/1118299.1118317
Zhou SYao BChen HZhu YCheng CHutton MCollins TSrinivasan SChou NSuaris P(2005)Improving the efficiency of static timing analysis with false pathsProceedings of the 2005 IEEE/ACM International conference on Computer-aided design10.5555/1129601.1129676(527-531)Online publication date: 31-May-2005
https://dl.acm.org/doi/10.5555/1129601.1129676
Zeng JAbadir MAbraham JAckland B(2002)False timing path identification using ATPG techniques and delay-based informationProceedings of the 39th annual Design Automation Conference10.1145/513918.514060(562-565)Online publication date: 10-Jun-2002
https://dl.acm.org/doi/10.1145/513918.514060
Zeng JAbadir MBhadra JAbraham J(2001)Full chip false timing path identificationProceedings of the conference on Design, automation and test in Europe10.5555/367072.367361(514-519)Online publication date: 13-Mar-2001
https://dl.acm.org/doi/10.5555/367072.367361
Chen H(2000)Static Timing Analysis with False PathsProceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors10.5555/557517.846845Online publication date: 17-Sep-2000
https://dl.acm.org/doi/10.5555/557517.846845
Blaauw DPanda RDas ADe Micheli G(2000)Removing user specified false paths from timing graphsProceedings of the 37th Annual Design Automation Conference10.1145/337292.337417(270-273)Online publication date: 1-Jun-2000
https://dl.acm.org/doi/10.1145/337292.337417
Fassnacht USchietke JDewilde PRammig FMusgrave G(1998)Timing analysis and optimization of a high-performance CMOS processor chipsetProceedings of the conference on Design, automation and test in Europe10.5555/368058.368165(325-330)Online publication date: 23-Feb-1998
https://dl.acm.org/doi/10.5555/368058.368165
Kukimoto YBrayton RChawla BBryant RRabaey J(1998)Hierarchical functional timing analysisProceedings of the 35th annual Design Automation Conference10.1145/277044.277197(580-585)Online publication date: 1-May-1998
https://dl.acm.org/doi/10.1145/277044.277197

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Removing user specified false paths from timing graphs