Accelerated design space pruning for CMP memory architectures: work-in-progress

We propose an approach to help the design space pruning process of CMP memory architectures by making several simplification hypotheses. Mainly, we assume that performance mostly depends on data locality and the closer a datum is in the memory architecture from the core requesting it, the better. We therefore focus on tracking memory accesses and data localities. Also, we associate an access cost reflecting relative technology performance with each cache in the targeted architecture. By collecting the number of accesses made by each core under a given workload to the memory banks and by using their respective access costs, a performance score can be computed. Architectures can then be compared by scores instead of using any concrete absolute metrics. The implementation of a trace-driven simulator incorporating these assumptions provided appreciable speedups at the expense of precision compared to other cycle-accurate simulators. But because of the limited accuracy, we try to identify under what conditions this method is adequate.