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HANNIBAL: an efficient tool for logic verification based on recursive learning

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Wolfgang KunzAuthors Info & Claims

ICCAD '93: Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

Pages 538 - 543

Published: 07 November 1993 Publication History

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References

[1]

Kunz W., Pradhan D. K.: "Recursive Learning: An Attractive Alternative to the Decision Tree for Test Generation in Digital Circuits", Proe. Intl. Test Conference, 1992, pp. 816-825.

Digital Library

Google Scholar

[2]

Ghosh A., Devadas S., Newton A. R.: "Sequential Logic Testing and Verification", Kluwer Academic Pub., 1992.

Digital Library

Google Scholar

[3]

Akers S.: "Binary Decision Diagrams", IEEE Transactions on Computers, vol. C-27, no. 6 June 1978, pp.509-516.

Google Scholar

[4]

Bryant R.: "Graph-Based Algorithms for Boolean Function Manipulation", IEEE Trans. on Computers, vol. C-35, no. 8, August 1986, pp. 677-691.

Digital Library

Google Scholar

[5]

Aas E. J., Klingsheim K., Steen T.: "Quantifying Design Quality: A Model and De,;ign Experiments", Proceedings of EURO ASIC 1992, pp. }t72-177.

Crossref

Google Scholar

[6]

Berman C. L., Trevyllian L. H.: "Functional Comparison of Logic Designs for VLSI Circuits", intl. Conf. on Comp.- Aided Design, 1989, pp. 456-459.

Google Scholar

[7]

Cerny E., Mauras C.: "Tautology Checking Using Cross- Controllability and Cross--Observability Relations", Intl. Conference on Computer-Aided Design, 1990, pp. 34-38.

Crossref

Google Scholar

[8]

Ktmz W., Pradhan D.K.: "Recursive Learning: A Precise Implication Procedure and its Application to Test Generation in Digital Circuits", accepted for publication in IEEE Trans. on Computer-Aided Design.

Google Scholar

[9]

Fujiwara H., Shimono T.: "On the Acceleration of Test Generation Algorithms", 13th Intl. Symp. on Fault Tolerant Comp., pp. 98-105, 1983.

Digital Library

Google Scholar

[10]

Schulz M., Trischler E., Sarfert T.: "SOCRATES: A Highly Efficient Automatic Test Pattern Generation System", IEEE Trans. on CA{), vol. 7, Jan. 88, pp. 126-137.

Digital Library

Google Scholar

[11]

Malik S. et al.: "Logic Verification using Binary Decision Diagrams in a Logic Synthesis Environment", Intl. Conference on Computer-Aided Design, 1988, pp. 6-9.

Crossref

Google Scholar

[12]

Jain J., Bitner J., Fussell D. S., Abraham J. A." "Probabilistic Verification of Roolean Functions", Journal of Formal Methods in Systems Design, vo1.1,1992, pp.61-115.

Google Scholar

[13]

Brglez F., Fujiwara H.: "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in FORTRAN", Special Session on the 1985 IEEE international Symposium on Circuits and Systems.

Google Scholar

[14]

Tromp G. J., van de Goor A. J.: "Logic Synthesis of 100- percent Testable Logic Networks", IEEE Intl. Conference on Computer-Design, Sept. 1991.

Digital Library

Google Scholar

[15]

Jain J. et al.: "Indexed BDDs: Algorithmic Advances in techniques to represent and verify Boolean functions", U. of Texas at Austin, UT-CERC-TR-JAA-93-02

Google Scholar

[16]

Mahlstedt U., Alt J.: "Shnulation of Non-Classical Faults on the Gate Level - The Fault Simulator COMSIM-" accepted for publication, Intl. Test Conference 1993.

Digital Library

Google Scholar

Cited By

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Goldberg EPiskac RTalupur M(2016)Equivalence checking by logic relaxationProceedings of the 16th Conference on Formal Methods in Computer-Aided Design10.5555/3077629.3077643(49-56)Online publication date: 3-Oct-2016
https://dl.acm.org/doi/10.5555/3077629.3077643
Cabodi GDipietro LMurciano MNocco S(2010)Finding Multiple Equivalence-Preserving Transformations in Combinational Circuits through Incremental-SATJournal of Electronic Testing: Theory and Applications10.1007/s10836-010-5144-026:2(261-278)Online publication date: 1-Apr-2010
https://dl.acm.org/doi/10.1007/s10836-010-5144-0
Case MKravets VMishchenko ABrayton RFix L(2008)Merging nodes under sequential observabilityProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391605(540-545)Online publication date: 8-Jun-2008
https://dl.acm.org/doi/10.1145/1391469.1391605
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Published In

ICCAD '93: Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

November 1993

781 pages

ISBN:0818644907

Chairmen:
Michael Lightner
Univ. of Colorado, Boulder
,
Jochen A. G. Jess
Eindhoven Univ. of Tech., Eindhoven, The Netherlands

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 07 November 1993

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ICCAD '93

Sponsor:

SIGDA
IEEE-CS

ICCAD '93: International Conference on Computer Aided Design

November 7 - 11, 1993

California, Santa Clara, USA

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

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Goldberg EPiskac RTalupur M(2016)Equivalence checking by logic relaxationProceedings of the 16th Conference on Formal Methods in Computer-Aided Design10.5555/3077629.3077643(49-56)Online publication date: 3-Oct-2016
https://dl.acm.org/doi/10.5555/3077629.3077643
Cabodi GDipietro LMurciano MNocco S(2010)Finding Multiple Equivalence-Preserving Transformations in Combinational Circuits through Incremental-SATJournal of Electronic Testing: Theory and Applications10.1007/s10836-010-5144-026:2(261-278)Online publication date: 1-Apr-2010
https://dl.acm.org/doi/10.1007/s10836-010-5144-0
Case MKravets VMishchenko ABrayton RFix L(2008)Merging nodes under sequential observabilityProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391605(540-545)Online publication date: 8-Jun-2008
https://dl.acm.org/doi/10.1145/1391469.1391605
Chatterjee SMishchenko ABrayton RKuehlmann ALevitan S(2007)On resolution proofs for combinational equivalenceProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278631(600-605)Online publication date: 4-Jun-2007
https://dl.acm.org/doi/10.1145/1278480.1278631
Zhu QKitchen NKuehlmann ASangiovanni-Vincentelli ASentovich E(2006)SAT sweeping with local observability don't-caresProceedings of the 43rd annual Design Automation Conference10.1145/1146909.1146970(229-234)Online publication date: 24-Jul-2006
https://dl.acm.org/doi/10.1145/1146909.1146970
Drechsler RFey G(2006)Automatic test pattern generationProceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems10.1007/11757283_2(30-55)Online publication date: 22-May-2006
https://dl.acm.org/doi/10.1007/11757283_2
Lajaunie RHsiao MLach JQu GIsmail Y(2005)An effective and efficient ATPG-based combinational equivalence checkerProceedings of the 15th ACM Great Lakes symposium on VLSI10.1145/1057661.1057722(248-253)Online publication date: 17-Apr-2005
https://dl.acm.org/doi/10.1145/1057661.1057722
Kuehlmann A(2004)Dynamic transition relation simplification for bounded property checkingProceedings of the 2004 IEEE/ACM International conference on Computer-aided design10.1109/ICCAD.2004.1382542(50-57)Online publication date: 7-Nov-2004
https://dl.acm.org/doi/10.1109/ICCAD.2004.1382542
Ratchev BHutton MBaeckler Gvan Antwerpen BTrimberger STessier R(2003)Verifying the correctness of FPGA logic synthesis algorithmsProceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays10.1145/611817.611837(127-135)Online publication date: 23-Feb-2003
https://dl.acm.org/doi/10.1145/611817.611837
Veneris ASmith AAbadir MYasuura H(2003)Logic verification based on diagnosis techniquesProceedings of the 2003 Asia and South Pacific Design Automation Conference10.1145/1119772.1119791(93-98)Online publication date: 21-Jan-2003
https://dl.acm.org/doi/10.1145/1119772.1119791
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