Article

Free access

Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip

Authors:

Bart Vermeulen,

Siddharth UmraniAuthors Info & Claims

NOCS '08: Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip

Pages 3 - 12

Published: 07 April 2008 Publication History

Abstract

We present a methodology to debug a SOC by concentrating on its communication. Our extended communication model includes a) multiple signal groups per interface protocol at each IP port, b) the handshakes per signal group (e.g. for command), and c) the handshakes within a signal group (e.g. for write and read data elements). As a result, our debug methodology is the first to offer debug control at three communication granularities: individual data elements in a message, messages (i.e. requests or responses), and entire transactions. Communication to distributed shared memories is supported in networks on chip (NOC) by transparently (de)multiplexing different master-slave channels based on the memory address, also called narrowcast. In this paper, we extend previous work on NOC debug that allowed per-connection debug (i.e. a master without differentiating between its slaves) to also support per-channel (i.e. per master-slave pair) debugging, also for narrowcast connections. This enables essential fine-grained debug control for multi-processor SOCs that use distributed-shared-memory communication. The debug infrastructure consists of hardware components, and a software API and library. We define the hard-ware infrastructure and the required changes to a NOC. Our architecture cleanly separates the monitoring and distribution of events from how they are interpreted and used, in terms of hardware and programming. We define a high-level software API for run-time user control. The debug methodology offers run-time programmable breakpoints, stopping, continuing, and single-stepping of distributed-shared memory communication at three granularities, at the cost of 2.5% NOC area increase and no speed penalty.

References

[1]

ARM. AMBA AXI Protocol Specification, June 2003.

[2]

C. Ciordas, T. Basten, A. Radulescu, K. Goossens, and J. van Meerbergen. An event-based monitoring service for networks on chip. ACM Transactions on Design Automation of Electronic Systems, Oct 2005.

Digital Library

[3]

C. Ciordas, K. Goossens, T. Basten, A. Radulescu, and A. Boon. Transaction monitoring in networks on chip: The on-chip run-time perspective. In Proc. Symposium on Industrial Embedded Systems (IES), Oct 2006.

[4]

P. Dahlgren, P. Dickinson, and I. Parulkar. Latch Divergency in Microprocessor Failure Analysis. In Proc. IEEE Int'l Test Conference, Sep/Oct 2003.

[5]

S. K. Goel and B. Vermeulen. Hierarchical data invalidation analysis for scan-based debug on multiple-clock system chips. In Proc. IEEE Int'l Test Conference (ITC), Oct 2002.

Digital Library

[6]

S. González Pestana, E. Rijpkema, A. Radulescu, K. Goossens, and O. P. Gangwal. Cost-performance tradeoffs in networks on chip: A simulation-based approach. In Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), Feb 2004.

Digital Library

[7]

K. Goossens, J. Dielissen, and A. Radulescu. The Æthereal network on chip: Concepts, architectures, and implementations. IEEE Design and Test of Computers, Sept/Oct 2005.

Digital Library

[8]

K. Goossens, B. Vermeulen, R. van Steeden, and M. Bennebroek. Transaction-based communication-centric debug. In Proc. Int'l Symposium on Networks on Chip (NOCS), May 2007.

Digital Library

[9]

A. Hansson and K. Goossens. Trade-offs in the configuration of a network on chip for multiple use-cases. In Proc. Int'l Symposium on Networks on Chip (NOCS), May 2007.

Digital Library

[10]

K. Holdbrook, S. Joshi, S. Mitra, J. Petolino, R. Raman, and M. Wong. microSPARC: A case study of scan-based debug. In Proc. IEEE Int'l Test Conference (ITC), 1994.

Digital Library

[11]

A. Hopkins and K. McDonald-Maier. Debug support for complex systems on-chip: A review. IEEE Proc. Computers and Digital Techniques, July 2006.

[12]

R. Leatherman and N. Stollon. An embedded debugging architecture for SoCs. IEEE Potentials, Feb-Mar 2005.

[13]

OCP International Partnership. Open core protocol specification, 2001.

[14]

Philips Semiconductors. Device Transaction Level (DTL) Protocol Specification. Version 2.2, July 2002.

[15]

G. Rootselaar and B. Vermeulen. Silicon Debug: Scan Chains Alone Are Not Enough. In Proc. IEEE Int'l Test Conference (ITC), Sept. 1999.

Digital Library

[16]

A. Radulescu, J. Dielissen, S. González Pestana, O. P. Gangwal, E. Rijpkema, P. Wielage, and K. Goossens. An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network programming. IEEE Transactions on CAD of Integrated Circuits and Systems, Jan 2005.

Digital Library

[17]

S. Tang and Q. Xu. A multi-core debug platform for NoCbased systems. In Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), 2007.

Digital Library

[18]

B. Vermeulen, K. Goossens, R. van Steeden, and M. Bennebroek. Communication-centric SOC debug using transactions. In Proc. European Test Symposium (ETS), May 2007.

Digital Library

[19]

B. Vermeulen, T. Waayers, and S. Goel. Core-based Scan Architecture for Silicon Debug. In Proc. IEEE Int'l Test Conference (ITC), Oct 2002.

Digital Library

Cited By

Seifi MEshghi M(2018)Clustered NOC, a suitable design for group communications in Network on ChipComputers and Electrical Engineering10.1016/j.compeleceng.2011.10.00338:1(82-95)Online publication date: 27-Dec-2018
https://dl.acm.org/doi/10.1016/j.compeleceng.2011.10.003
Cunha MFournel NPétrot F(2015)Collecting traces in dynamic binary translation based virtual prototyping platformsProceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools10.1145/2693433.2693437(1-6)Online publication date: 19-Jan-2015
https://dl.acm.org/doi/10.1145/2693433.2693437
Fiorin LPalermo GSilvano CPalesi MKumar SLu ZOgras U(2010)A monitoring system for NoCsProceedings of the Third International Workshop on Network on Chip Architectures10.1145/1921249.1921257(25-30)Online publication date: 4-Dec-2010
https://dl.acm.org/doi/10.1145/1921249.1921257
Show More Cited By

Index Terms

Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Multiple instruction, multiple data
2. Hardware

Recommendations

Exploration of distributed shared memory architectures for NoC-based multiprocessors

Multiprocessor system-on-chip (MP-SoC) platforms represent an emerging trend for embedded multimedia applications. To enable MP-SoC platforms, scalable communication-centric interconnect fabrics, such as networks-on-chip (NoCs), have been recently ...
Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors
CODES+ISSS '09: Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis

Increasing application complexity and improvements in process technology have today enabled chip multiprocessors (CMPs) with tens to hundreds of cores on a chip. Networks on Chip (NoCs) have emerged as scalable communication fabrics that can support ...
Flexible Reconfigurable On-chip Networks for Multi-core SoCs
HEART '18: Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies

Multi and many-core embedded SoCs (System-on-Chip) provide key solutions to meet the extraordinary demands of current and future applications. This fact becomes critical when the chip design dives to the limitation of sub-nanometer technologies that ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image Guide Proceedings

NOCS '08: Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip

April 2008

213 pages

ISBN:9780769530987

Publisher

IEEE Computer Society

United States

Publication History

Published: 07 April 2008

Author Tags

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

8
Total Citations
View Citations
88
Total Downloads

Downloads (Last 12 months)21
Downloads (Last 6 weeks)5

Reflects downloads up to 12 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Seifi MEshghi M(2018)Clustered NOC, a suitable design for group communications in Network on ChipComputers and Electrical Engineering10.1016/j.compeleceng.2011.10.00338:1(82-95)Online publication date: 27-Dec-2018
https://dl.acm.org/doi/10.1016/j.compeleceng.2011.10.003
Cunha MFournel NPétrot F(2015)Collecting traces in dynamic binary translation based virtual prototyping platformsProceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools10.1145/2693433.2693437(1-6)Online publication date: 19-Jan-2015
https://dl.acm.org/doi/10.1145/2693433.2693437
Fiorin LPalermo GSilvano CPalesi MKumar SLu ZOgras U(2010)A monitoring system for NoCsProceedings of the Third International Workshop on Network on Chip Architectures10.1145/1921249.1921257(25-30)Online publication date: 4-Dec-2010
https://dl.acm.org/doi/10.1145/1921249.1921257
Goossens KHansson ASapatnekar S(2010)The aethereal network on chip after ten yearsProceedings of the 47th Design Automation Conference10.1145/1837274.1837353(306-311)Online publication date: 13-Jun-2010
https://dl.acm.org/doi/10.1145/1837274.1837353
Fiorin LPalermo GSilvano CBenini LDe Micheli GAl-Hashimi BMueller W(2009)MPSoCs run-time monitoring through networks-on-chipProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874756(558-561)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874756
Goossens KVermeulen BNejad ABenini LDe Micheli GAl-Hashimi BMueller W(2009)A high-level debug environment for communication-centric debugProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874669(202-207)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874669
Hansson AGoossens KRosenstiel WWakabayashi K(2009)An on-chip interconnect and protocol stack for multiple communication paradigms and programming modelsProceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis10.1145/1629435.1629450(99-108)Online publication date: 11-Oct-2009
https://dl.acm.org/doi/10.1145/1629435.1629450
Fiorin LPalermo GSilvano CGebotys CMartin G(2008)A security monitoring service for NoCsProceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis10.1145/1450135.1450180(197-202)Online publication date: 19-Oct-2008
https://dl.acm.org/doi/10.1145/1450135.1450180

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Media

Figures

Other

Tables

View Table of Contents