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Performance evaluation of exclusive cache hierarchies

Published: 10 March 2004 Publication History

Abstract

Memory hierarchy performance, specifically cache memory capacity, is a constraining factor in the performance of modern computers. This paper presents the results of two-level cache memory simulations and examines the impact of exclusive caching on system performance. Exclusive caching enables higher capacity with the same cache area by eliminating redundant copies. The experiments presented compare an exclusive cache hierarchy with an inclusive cache hierarchy utilizing similar L1 and L2 parameters. Experiments indicate that significant performance advantages can be gained for some benchmark through the use of an exclusive organization. The performance differences are illustrated using the L2 cache misses and execution time metrics. The most significant improvement shown is a 16% reduction in execution time, with an average reduction of 8% for the smallest cache configuration tested. With equal size victim buffer and victim cache for exclusive and inclusive cache hierarchies respectively, some benchmarks show increased execution time for exclusive caches because a victim cache can reduce conflict misses significantly while a victim buffer can introduce worst-case penalties. Considering the inconsistent performance improvement, the increased complexity of an exclusive cache hierarchy needs to be justified based upon the specifics of the application and system.

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    cover image Guide Proceedings
    ISPASS '04: Proceedings of the 2004 IEEE International Symposium on Performance Analysis of Systems and Software
    March 2004
    169 pages
    ISBN:0780383850

    Publisher

    IEEE Computer Society

    United States

    Publication History

    Published: 10 March 2004

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    • (2021)Zero inclusion victimProceedings of the 48th Annual International Symposium on Computer Architecture10.1109/ISCA52012.2021.00015(71-84)Online publication date: 14-Jun-2021
    • (2019)The impact of cache inclusion policies on cache management techniquesProceedings of the International Symposium on Memory Systems10.1145/3357526.3357547(428-438)Online publication date: 30-Sep-2019
    • (2017)A study of partitioned DIMM tree management for multimedia server systemsMultimedia Tools and Applications10.1007/s11042-016-3382-676:17(17937-17954)Online publication date: 1-Sep-2017
    • (2016)LAPACM SIGARCH Computer Architecture News10.1145/3007787.300114844:3(103-114)Online publication date: 18-Jun-2016
    • (2016)LAPProceedings of the 43rd International Symposium on Computer Architecture10.1109/ISCA.2016.19(103-114)Online publication date: 18-Jun-2016
    • (2015)Placement of Linked Dynamic Data Structures over Heterogeneous Memories in Embedded SystemsACM Transactions on Embedded Computing Systems10.1145/265620814:2(1-30)Online publication date: 17-Feb-2015
    • (2013)ARIACM Transactions on Architecture and Code Optimization10.1145/254369710:4(1-19)Online publication date: 1-Dec-2013
    • (2013)Temporal-based multilevel correlating inclusive cache replacementACM Transactions on Architecture and Code Optimization10.1145/2541228.255529010:4(1-24)Online publication date: 1-Dec-2013
    • (2012)FLEXclusionProceedings of the 39th Annual International Symposium on Computer Architecture10.5555/2337159.2337196(321-332)Online publication date: 9-Jun-2012
    • (2012)FLEXclusionACM SIGARCH Computer Architecture News10.1145/2366231.233719640:3(321-332)Online publication date: 9-Jun-2012
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