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View all- Chen TCengiz ASarrafzadeh MBanerjee PRoy K(2000)Measuring routing congestion for multi-layer global routingProceedings of the 10th Great Lakes symposium on VLSI10.1145/330855.330968(59-62)Online publication date: 2-Mar-2000
- Nakatake SFujiyoshi KMurata HKajitani YRutenbar ROtten R(1997)Module placement on BSG-structure and IC layout applicationsProceedings of the 1996 IEEE/ACM international conference on Computer-aided design10.5555/244522.244865(484-491)Online publication date: 1-Jan-1997
- Hagen LHuang DKahng APreas B(1995)Quantified suboptimality of VLSI layout heuristicsProceedings of the 32nd annual ACM/IEEE Design Automation Conference10.1145/217474.217532(216-221)Online publication date: 1-Jan-1995