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Multi-clock SoC design using protocol conversion

Published: 20 April 2009 Publication History

Abstract

The automated design of SoCs from pre-selected IPs that may require different clocks is challenging because of the following issues. Firstly, protocol mismatches between IPs need to be resolved automatically before IPs are integrated. Secondly, the presence of multiple clocks makes the protocol conversion even more difficult. Thirdly, it is desirable that the resulting integration is correct-by-construction, i.e., the resulting SoC satisfies given system-level specifications. All of these issues have been studied extensively, although not in a unifying manner. In this paper we propose a framework based on protocol conversion that addresses all these issues. We have extensively studied many SoC design problems and show that the proposed methodology is capable of handling them better than other known approaches. A significant contribution of the proposed approach is that it nicely generalizes many existing techniques for formal SoC design and integrates them into a single approach.

References

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R. Sinha, P. S. Roop, S. Basu, and Z. Salcic, "A module checking based converter synthesis approach for socs," in VLSI Design Conference. IEEE, 2008, pp. 492--501.
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R. Sinha, P. S. Roop, S. Basu, and Z. Salcic, "An Approach for Resolving Control and Data Mismatches in SoCs," School of Engineering, University of Auckland, Report 667, 2008.
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K. Avnit, V. D'Silva, A. Sowmya, S. Ramesh, and S. Parameswaran, "A formal approach to the protocol converter problem," in DATE, March 2008, pp. 294--299.
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Cited By

View all
  • (2015)Automated Synthesis of Protocol Converters with BALM-IIRevised Selected Papers of the SEFM 2015 Collocated Workshops on Software Engineering and Formal Methods - Volume 950910.1007/978-3-662-49224-6_23(281-296)Online publication date: 7-Sep-2015
  • (2014)A Formal Approach to Incremental Converter Synthesis for System-on-Chip DesignACM Transactions on Design Automation of Electronic Systems10.1145/266334420:1(1-30)Online publication date: 18-Nov-2014
  • (2012)Correct-by-construction multi-component SoC designProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492871(647-652)Online publication date: 12-Mar-2012
  • Show More Cited By

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Information & Contributors

Information

Published In

cover image ACM Conferences
DATE '09: Proceedings of the Conference on Design, Automation and Test in Europe
April 2009
1776 pages
ISBN:9783981080155

Sponsors

  • EDAA: European Design Automation Association
  • ECSI
  • EDAC: Electronic Design Automation Consortium
  • SIGDA: ACM Special Interest Group on Design Automation
  • The IEEE Computer Society TTTC
  • The IEEE Computer Society DATC
  • The Russian Academy of Sciences: The Russian Academy of Sciences

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European Design and Automation Association

Leuven, Belgium

Publication History

Published: 20 April 2009

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  • Research-article

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DATE '09
Sponsor:
  • EDAA
  • EDAC
  • SIGDA
  • The Russian Academy of Sciences

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

View all
  • (2015)Automated Synthesis of Protocol Converters with BALM-IIRevised Selected Papers of the SEFM 2015 Collocated Workshops on Software Engineering and Formal Methods - Volume 950910.1007/978-3-662-49224-6_23(281-296)Online publication date: 7-Sep-2015
  • (2014)A Formal Approach to Incremental Converter Synthesis for System-on-Chip DesignACM Transactions on Design Automation of Electronic Systems10.1145/266334420:1(1-30)Online publication date: 18-Nov-2014
  • (2012)Correct-by-construction multi-component SoC designProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492871(647-652)Online publication date: 12-Mar-2012
  • (2009)Tight WCRT analysis of synchronous C programsProceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems10.1145/1629395.1629424(205-214)Online publication date: 11-Oct-2009

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