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BSG-Route: a length-matching router for general topology

Published: 10 November 2008 Publication History

Abstract

Length-matching routing is a very important issue for PCB routing. Previous length-matching routers [1]--[3] all have assumptions on the routing topology whereas practical designs may be free of any topological constraint. In this paper, we propose a router that deals with general topology. Unlike previous routers, our router does not impose any restriction on the routing topology. Moreover, our router is gridless. Its performance does not depend on the routing grid size of the input while routers in [1]--[3] do. This is a big advantage because modern PCB routing configurations usually imply huge routing grids. The novelty of this work is that we view the length-matching routing problem as an area assignment problem and use a placement structure, Bounded-Sliceline Grid (BSG) [4], to help solving the problem. Experimental results show that our router can handle practical designs that previous routers can't handle. For designs that they could handle, our router runs much faster. For example, in one of our data, we obtain the result in 88 seconds while the router in [3] takes more than one day.

References

[1]
M. M. Ozdal and M. D. F. Wong, "Algorithmic study of single-layer bus routing for high-speed boards," IEEE Trans. Computer-Aided Design, vol. 25, no. 3, pp. 490--503, Mar. 2006.
[2]
Y. Kubo, H. Miyashita, Y. Kajitani, and K. Takeishi, "Equidistance routing in high-speed VLSI layout design," Integration, the VLSI Journal, vol. 38, no. 3, pp. 439--449, Jan. 2005.
[3]
M. M. Ozdal and M. D. F. Wong, "A length-matching routing algorithm for high-performance printed circuit boards," IEEE Trans. Computer-Aided Design, vol. 25, no. 12, Dec. 2006.
[4]
S. Nakatake, K. Fujiyoshi, H. Murata, and Y. Kajitani, "Module packing based on the BSG-structure and IC layout applications," IEEE Trans. Computer-Aided Design, vol. 17, no. 6, June 1998.
[5]
D. Wiens, "Printed circuit board routing at the threshold," in White Paper. Mentor Graphics, 2000. {Online}. Available: http://www.mentor.com/products/pcb/expedition/techpubs/mentorpaper_626
[6]
L. W. Ritchey and J. Zasio, Right the First Time, A Practical Handbook on High Speed PCB and System Design, K. J. Knack, Ed. Speeding Edge, 2003.
[7]
L. W. Ritchey, "Busses: What are they and how do they work?" in Printed Circuit Design Magazine, Dec. 2000. {Online}. Available: http://www.speedingedge.com/PDF-Files/busses.pdf
[8]
T. Yan and M. D. F. Wong, "Untangling twisted nets for bus routing," in Proc. IEEE/ACM Intl. Conf. on Computer-Aided Design, 2007, pp. 396--400.
[9]
lp_solve: an open source linear programming solver. {Online}. Available: http://sourceforge.net/projects/lpsolve

Cited By

View all
  • (2019)A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus RoutingProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317740(1-6)Online publication date: 2-Jun-2019
  • (2016)Novel CMOS RFIC layout generation with concurrent device placement and fixed-length microstrip routingProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2898052(1-6)Online publication date: 5-Jun-2016
  • (2013)Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuitsProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488740(1-6)Online publication date: 29-May-2013
  • Show More Cited By

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cover image ACM Conferences
ICCAD '08: Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
November 2008
855 pages
ISBN:9781424428205

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IEEE Press

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Published: 10 November 2008

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ASE08
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ASE08: The International Conference on Computer-Aided Design
November 10 - 13, 2008
California, San Jose

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

View all
  • (2019)A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus RoutingProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317740(1-6)Online publication date: 2-Jun-2019
  • (2016)Novel CMOS RFIC layout generation with concurrent device placement and fixed-length microstrip routingProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2898052(1-6)Online publication date: 5-Jun-2016
  • (2013)Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuitsProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488740(1-6)Online publication date: 29-May-2013
  • (2012)Maze routing algorithms with exact matching constraints for analog and mixed signal designsProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429409(130-136)Online publication date: 5-Nov-2012
  • (2011)Obstacle-aware length-matching bus routingProceedings of the 2011 international symposium on Physical design10.1145/1960397.1960412(61-68)Online publication date: 27-Mar-2011
  • (2010)Recent research development in PCB layoutProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133514(398-403)Online publication date: 7-Nov-2010
  • (2010)Obstacle-aware longest path using rectangular pattern detouring in routing gridsProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899783(287-292)Online publication date: 18-Jan-2010
  • (2010)Optimal simultaneous pin assignment and escape routing for dense PCBsProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899781(275-280)Online publication date: 18-Jan-2010
  • (2010)Two-sided single-detour untangling for bus routingProceedings of the 47th Design Automation Conference10.1145/1837274.1837325(206-211)Online publication date: 13-Jun-2010
  • (2009)Optimal layer assignment for escape routing of busesProceedings of the 2009 International Conference on Computer-Aided Design10.1145/1687399.1687444(245-248)Online publication date: 2-Nov-2009
  • Show More Cited By

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