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Minimum padding to satisfy short path constraints

Published: 07 November 1993 Publication History
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References

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M.R.C.M. Berkelaar and J. A. G. Jess. Private communication. June, 1993.
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C.L. Berman, J. L. Carter, and K. E Day. The Fanout Problem: From Theory to Practice. In Advanced Research in VLSI: Proceedings of the 1989 Decennial Caltech Conference, pages 69-99, 1989.
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J. E Fishbum. A Depth-Decreasing Heuristic for Combinational Logic. In Proceedings of the Design Automation Conference, pages 361-364,1990.
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J. P. Fishbum. LA'ITIS: An Iterative Speedup Heuristic for Mapped Logic. In Proceedings of the Design Automation Conference, pages 488-491,1992.
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M.R. Garey and D. S. Johnson. Computers and Intractability A Guide to the Theory of NP-Completeness. W. H. Freeman and Company, 1979.
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P.G. Paulin and F. Poirot. Logic Decompostion Algorithms for the Timing Optimization of Multi-Level Logic. In Proceedings of the International Conference on Computer Destgn, pages 329-33, 1989.
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N. Shenoy, R. K. Brayton, and A. Sangi~vanni-VincenteUi" Resynthesis of Multi-Phase Pipelines. In Proceedings of the Design Automation Conference, 1993.
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N. V. Shenoy. Timing Issues in Sequential Circuits. PhD thesis, University of California, Berkeley, 1993.
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K.J. Singh, A. R. Wang, R. K. Brayton, andA. Sangiovanni- V'mcentelli. Timing Optimization of Combinational Logic. In Proceedings of the International Conference on Computer-Aided Design, pages 282-285, 1988.
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  • (2021)A Variation-aware Hold Time Fixing Methodology for Single Flux Quantum Logic CircuitsACM Transactions on Design Automation of Electronic Systems10.1145/346028926:6(1-17)Online publication date: 1-Aug-2021
  • (2017)Power and Area Efficient Hold Time Fixing by Free Metal Segment AllocationProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062303(1-6)Online publication date: 18-Jun-2017
  • (2015)Clock Period Minimization with Minimum Leakage PowerACM Transactions on Design Automation of Electronic Systems10.1145/277895421:1(1-33)Online publication date: 2-Dec-2015
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cover image ACM Conferences
ICCAD '93: Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
November 1993
781 pages
ISBN:0818644907

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IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 07 November 1993

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ICCAD '93
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ICCAD '93: International Conference on Computer Aided Design
November 7 - 11, 1993
California, Santa Clara, USA

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

View all
  • (2021)A Variation-aware Hold Time Fixing Methodology for Single Flux Quantum Logic CircuitsACM Transactions on Design Automation of Electronic Systems10.1145/346028926:6(1-17)Online publication date: 1-Aug-2021
  • (2017)Power and Area Efficient Hold Time Fixing by Free Metal Segment AllocationProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062303(1-6)Online publication date: 18-Jun-2017
  • (2015)Clock Period Minimization with Minimum Leakage PowerACM Transactions on Design Automation of Electronic Systems10.1145/277895421:1(1-33)Online publication date: 2-Dec-2015
  • (2014)Leakage-power-aware clock period minimizationProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616991(1-6)Online publication date: 24-Mar-2014
  • (2014)On Timing ClosureProceedings of the 51st Annual Design Automation Conference10.1145/2593069.2593171(1-6)Online publication date: 1-Jun-2014
  • (2013)Low-power timing closure methodology for ultra-low voltage designsProceedings of the International Conference on Computer-Aided Design10.5555/2561828.2561964(697-704)Online publication date: 18-Nov-2013
  • (2013)PushPullProceedings of the 2013 ACM International symposium on Physical Design10.1145/2451916.2451928(50-57)Online publication date: 24-Mar-2013
  • (2011)Fast statistical timing analysis for circuits with post-silicon tunable clock buffersProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132354(111-117)Online publication date: 7-Nov-2011
  • (2011)Re-synthesis for cost-efficient circuit-level timing speculationProceedings of the 48th Design Automation Conference10.1145/2024724.2024760(158-163)Online publication date: 5-Jun-2011
  • (2010)Statistical analysis of hold time violationsJournal of Computational Electronics10.1007/s10825-010-0322-y9:3-4(114-121)Online publication date: 1-Dec-2010
  • Show More Cited By

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