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Engineering change using spare cells with constant insertion

Published: 05 November 2007 Publication History

Abstract

In the VLSI design process, a design implementation often needs to be corrected because of new specifications or design constraint violations. This correction process is referred to as engineering change (EC). Usually, an EC problem is resolved by using spare cells, which have been inserted into the unused spaces of a chip. In this paper, we propose an iterative method to generate feasible mapping solutions for an EC problem considering spare cells whose inputs may be tied to Vdd or Gnd, called constant insertion. Applying constant insertion can increase a cell's flexibility in aspect of functionalities, so far-away spare cells need not be used just for some specific functionality. Our experimental results show that the area in which there are enough spare cells for a mapping solution with constant insertion is only 82% of the area without constant insertion.

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Cited By

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  • (2012)Timing ECO optimization using metal-configurable gate-array spare cellsProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228505(802-807)Online publication date: 3-Jun-2012
  • (2011)Timing ECO optimization via Bézier curve smoothing and fixability identificationProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132487(742-746)Online publication date: 7-Nov-2011
  • (2011)Match and replaceProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132421(383-388)Online publication date: 7-Nov-2011
  • Show More Cited By

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Information & Contributors

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Published In

cover image ACM Conferences
ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
November 2007
933 pages
ISBN:1424413826
  • General Chair:
  • Georges Gielen

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IEEE Press

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Published: 05 November 2007

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ICCAD '07 Paper Acceptance Rate 139 of 510 submissions, 27%;
Overall Acceptance Rate 457 of 1,762 submissions, 26%

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View all
  • (2012)Timing ECO optimization using metal-configurable gate-array spare cellsProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228505(802-807)Online publication date: 3-Jun-2012
  • (2011)Timing ECO optimization via Bézier curve smoothing and fixability identificationProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132487(742-746)Online publication date: 7-Nov-2011
  • (2011)Match and replaceProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132421(383-388)Online publication date: 7-Nov-2011
  • (2011)A robust ECO engine by resource-constraint-aware technology mapping and incremental routing optimizationProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950896(382-387)Online publication date: 25-Jan-2011
  • (2009)Matching-based minimum-cost spare cell selection for design changesProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1630018(408-411)Online publication date: 26-Jul-2009
  • (2009)New spare cell design for IR drop minimization in Engineering Change OrderProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1630017(402-407)Online publication date: 26-Jul-2009
  • (2009)A metal-only-ECO solver for input-slew and output-loading violationsProceedings of the 2009 international symposium on Physical design10.1145/1514932.1514974(191-198)Online publication date: 29-Mar-2009

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