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- research-articleNovember 2024
PROTECTS: Progressive Rtl Obfuscation with ThrEshold Control Technique during architectural Synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 30, Issue 1Article No.: 7, Pages 1–34https://doi.org/10.1145/3701032Due to the supply chain globalization of the semiconductor industry, securing heterogeneous System-on-Chip (SoC) is becoming necessary. A malicious alteration, inserting Hardware Trojan, infringement, or counterfeiting of design via Reverse Engineering (...
- research-articleMay 2020
Large-scale Functional Integration, Rather than Functional Dissociation along Dorsal and Ventral Streams, Underlies Visual Perception and Action
Journal of Cognitive Neuroscience (JOCN), Volume 32, Issue 5Pages 847–861https://doi.org/10.1162/jocn_a_01527Visual dual-stream theory posits that two distinct neural pathways of specific functional significance originate from primary visual areas and reach the inferior temporal (ventral) and posterior parietal areas (dorsal). However, there are several ...
- ArticleDecember 2019
Empirical Mode Decomposition Algorithms for Classification of Single-Channel EEG Manifesting McGurk Effect
- Arup Kumar Pal,
- Dipanjan Roy,
- G. Vinodh Kumar,
- Bipra Chatterjee,
- L. N. Sharma,
- Arpan Banerjee,
- Cota Navin Gupta
AbstractBrain state classification using electroencephalography (EEG) finds applications in both clinical and non-clinical contexts, such as detecting sleep states or perceiving illusory effects during multisensory McGurk paradigm, respectively. Existing ...
- research-articleAugust 2018
Low-Cost Obfuscated JPEG CODEC IP Core for Secure CE Hardware
IEEE Transactions on Consumer Electronics (ITOCE), Volume 64, Issue 3Pages 365–374https://doi.org/10.1109/TCE.2018.2852265A novel approach for obfuscated JPEG compression/decompression (CODEC) IP core design methodology, suitable for use in re-usable IP core designs, is presented. This incorporates structural obfuscation for architecture or structure hiding from an ...
- research-articleAugust 2017
Automated low cost scheduling driven watermarking methodology for modern CAD high-level synthesis tools
Advances in Engineering Software (ADES), Volume 110, Issue CPages 26–33https://doi.org/10.1016/j.advengsoft.2017.03.008Novel low cost scheduling driven watermarking methodology for CAD high level synthesis tools.Proposed watermarking methodology is based on a robust signature encoding that incurs zero hardware overhead and minimal delay overhead resulting into extremely ...
- research-articleJune 2017
Low overhead symmetrical protection of reusable IP core using robust fingerprinting and watermarking during high level synthesis
Future Generation Computer Systems (FGCS), Volume 71, Issue CPages 89–101https://doi.org/10.1016/j.future.2017.01.021Intellectual Property (IP) core used in computing system-on-chip provides a unique blend of yielding enhanced design productivity with reduced design cycle time. However, leveraging benefits of IP core require protection against threats from both ...