An Efficient Ensemble Binarized Deep Neural Network on Chip with Perception-Control Integrated †
<p>Network topology of EBDN model, in which essential architecture is a 6-layer network with 2 residual blocks and two separate fully-connected layers for judgement of steering angle and prediction of collision probability, respectively. The <span class="html-italic">f</span> as indicated above is the pooling or convolution kernel’s size, and the <span class="html-italic">s</span> is the corresponding stride.</p> "> Figure 2
<p>The sky blue box contains Udacity images which uses to learn and control steering angles, the orange box includes no-collision and corresponding collision frames which are collected to predict the probability of collision.</p> "> Figure 3
<p>Schematic diagram of EBDN model. Each EBDN performs a separate training on each sample set generated by the bagging method and finally fuses all outputs through an ensemble mechanism to obtain the final results.</p> "> Figure 4
<p>The accuracy of 64-128-128 BMLP models on MNIST when we change the number of aggregated BMLPs from 1 to 8.</p> "> Figure 5
<p>The overall architecture of EBDNoC, which mainly consists of two ARM cores, a neural network co-processor, and other peripherals. EBDNoC co-processor uses several Parallel pipelines to complete the ensemble calculation of the EBDN model. The bagging PE is in charge of aggregating the parallel outputs of EBDNPs.</p> "> Figure 6
<p>The block diagram of computing arrays, which consist of CDC unit, CONV unit, and BAP unit. The CDC unit is applied to cache input feature maps from last layer and generate convolution calculation data, CONV unit is responsible for convolution operation, the operations of batch normalization, activation, and pooling are performed in BAP unit.</p> "> Figure 7
<p>The overall architecture of XNOR-Popcount computing circuit unit, and the right purple block represents its internal architecture of Popcount-36(25) submodule.</p> "> Figure 8
<p>The structure of feature map buffer. The <math display="inline"><semantics> <mrow> <mpadded height="0pt" depth="0pt"> <mi>w</mi> </mpadded> <mo>_</mo> <mi>b</mi> <mi>u</mi> <mi>f</mi> <mo>_</mo> <mi>s</mi> <mi>e</mi> <mi>l</mi> </mrow> </semantics></math> and <math display="inline"><semantics> <mrow> <mi>r</mi> <mo>_</mo> <mi>b</mi> <mi>u</mi> <mi>f</mi> <mo>_</mo> <mi>s</mi> <mi>e</mi> <mi>l</mi> </mrow> </semantics></math> signals are the choice signals for the write buffer and the read buffer, respectively.</p> "> Figure 9
<p>The hardware architecture design of bagging PE.</p> "> Figure 10
<p>The performance of EBDN model variation as the number of aggregated subnetworks from 1 to 8. (<b>a</b>) EVA metric; (<b>b</b>) RMSE metric; (<b>c</b>) classification accuracy; (<b>d</b>) F-1 score.</p> ">
Abstract
:1. Introduction
- We propose an EBDN model, which overcomes the accuracy bottleneck of a single network by integrating several binarized DroNets with ultra-low memory footprint, and can dramatically speed up the inference process of the model when compared to full precision neural networks. Moreover, the proposed method can be easily extended to other CNN designs.
- For our proposed EBDNoC system, we design a dedicated on-chip hardware streaming architecture with a fully pipelined data path and configurable degree of parallelism for ensemble architectures.
- We also evaluate the performance of our proposed hardware architecture on FPGA achieving comparable system throughput, energy and resource efficiency, while can provide the trade-off between model performance and hardware resource.
2. Related Work
2.1. Quantized Neural Networks
2.2. DCNNs Deployed on FPGAs
3. The Proposed Model
3.1. Perception-Control Integrated Model
3.2. Binarized Neural Network
3.3. Ensemble Learning Method
- 1.
- Compared to the original full-precision model, the EBDN model achieves a similar accuracy on Udacity and Collision datasets with much less memory footprint, which dramatically reduces the power consumption of the hardware. In addition, the binarized method eliminates the original inefficient CONV operation and replaces it with high energy-efficiency bitwise operation.
- 2.
- The flexible configurable number of subnetworks provides a trade-off between performance and resources for on-chip implementations, and, in fact, our network is suitable for many applications beyond the autonomous navigation of UAVs system mentioned in this paper.
4. Hardware Architecture Design
4.1. Overall Architecture
4.2. Computing Array
4.2.1. Convolution Data Cache
4.2.2. CONV Unit
4.2.3. BAP Unit
4.3. Memory System Design
4.3.1. Quantization Strategy
4.3.2. Feature Map Buffer
4.3.3. Memory Organization for Weights
4.4. Bagging PE
5. Experiments and Results
5.1. Evaluation of EBDN Model
5.2. Comparison with CPU and GPU
5.3. Performance of Hardware Architecture
6. Conclusions
Author Contributions
Funding
Institutional Review Board Statement
Informed Consent Statement
Data Availability Statement
Conflicts of Interest
Abbreviations
EBDN | Ensemble Binarized DroNet |
FPGA | Field Programmable Gate Array |
DCNN | Deep Convolutional Neural Network |
UAV | Unmanned Aerial Vehicle |
SoC | System on Chip |
BRAM | Block RAM |
BNN | Binary Neural Network |
VDMA | Video Direct Memory Access |
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Layer | Weight | Activation | CONV Bias | BN Bias | Multiplier Factor | Mem.parameters (bits) |
---|---|---|---|---|---|---|
1 (CONV) | (0, 8) | (8, 0) | (0, 0) | - | - | 6400 |
2 (CONV) | (1, 0) | (1, 0) | (0, 0) | (16, 0) | (16, 0) | 10,240 |
3 (CONV) | (1, 0) | (1, 0) | (0, 0) | (16, 0) | (16, 0) | 10,240 |
3 (RCONV) | (0, 8) | (8, 0) | (0, 0) | - | - | 8192 |
4 (CONV) | (1, 0) | (1, 0) | (0, 0) | (16, 0) | (16, 0) | 19,456 |
5 (CONV) | (1, 0) | (1, 0) | (0, 0) | (16, 0) | (16, 0) | 38,912 |
5 (RCONV) | (0, 8) | (8, 0) | (0, 0) | - | - | 16,384 |
6 (FC) | (0, 8) | (8, 0) | (0, 8) | - | - | 25,096 |
6 (FC) | (0, 8) | (8, 0) | (0, 8) | - | - | 25,096 |
Total | - | - | - | - | - | 0.02 (MB) |
Model | [48] | [42] | [47] | [14] | [15] | EBDN (Ours) |
---|---|---|---|---|---|---|
EVA | 0.672 | 0.795 | 0.712 | 0.737 | 0.748 | 0.712 |
RMSE | 0.125 | 0.097 | 0.119 | 0.109 | 0.111 | 0.114 |
Avg. accuracy | 91.2% | 96.6% | 92.7% | 95.4% | 95.9% | 95.6% |
F-1 score | 0.823 | 0.921 | 0.847 | 0.901 | 0.902 | 0.900 |
Num. Layers | 6 | 50 | 16 | 8 | 8 | 6 |
Memory (MB) | 0.221 | 99.182 | 28.610 | 1.221 | 0.610 | 0.16 |
Precision | 32-bit | 32-bit | 32-bit | 32-bit | 16-bit | 1-bit, 8-bit |
Speed (FPS) | 23 | 7 | 12 | 20 | 18 | 285 |
Device | Intel Core i7 | Intel Core i7 | Intel Core i7 | Intel Core i7 | GAP8 SoC | Zynq 7Z100 |
Device | Intel Xeon Platinum 8269CY | Nvidia GTX2080 Ti | Nvidia Jetson TX2 | Zynq 7Z100 |
---|---|---|---|---|
Technology | 14 nm | 12 nm | 16 nm | 28 nm |
Clock Freq. (MHz) | 2.5 K | 1.35 K | 1.3 K | 100 |
Precision | 32 bits float | 32 bits float | 32 bits float | 1 bit, 8 bits fixed |
FPS (frame/s) | 32.2 | 167.1 | 56.8 | 285.3 |
Speedup | 1.0× | 5.19× | 1.76× | 8.86× |
Power (W) | 205 | 53 | 4.56 | 6.48 |
Energy efficiency (FPS/W) | 0.16 | 3.15 | 12.46 | 44.03 |
Zhao [49] | Cho [40] | Zhang [50] | Lu [35] | Li [51] | Ours | |
---|---|---|---|---|---|---|
FPGA Device | XC7Z020 | XCZU7EV | XC7Z035 | ZCU102 | XC7Z100 | XC7Z100 |
Frequency (MHz) | 143 | 371 | 200 | 200 | 200 | 200 |
LUTs | 46.9 K | 4.8 K | 82 K | 600 K | 136.9 K | 43 K |
DSPs | 3 | 2 | 192 | 2520 | 1152 | 12 |
BRAMs | N/A | 89 | 369 | 1824 | 912 | 286 |
Image Size | 32 × 32 | 224 × 224 | 1024 × 1024 | 224 × 224 | 416×416 | 100 × 100 |
CNN Model | Cifar10 | VGG-16 | YOLOv2 | Alexnet | VGG-16 | EBDN |
Precision | 1-bit, 2-bit | 1-bit | 8-bit | 16-bit | 16-bit | 1-bit, 8-bit |
Throughput (GOPS) | 207.8 | 177.68 | 111.5 | 854.6 | 452.8 | 439.1 |
Power (W) | 4.7 | 0.711 | 5.96 | 23.6 | 19.52 | 2.11 |
Resource efficiency (GOPS/kLUTs) | 4.43 | 37.02 | 1.36 | 1.424 | 3.31 | 10.21 |
Power efficiency (GOPS/W) | 44.2 | 250 | 18.71 | 36.2 | 23.20 | 208.1 |
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He, W.; Yang, D.; Peng, H.; Liang, S.; Lin, Y. An Efficient Ensemble Binarized Deep Neural Network on Chip with Perception-Control Integrated. Sensors 2021, 21, 3407. https://doi.org/10.3390/s21103407
He W, Yang D, Peng H, Liang S, Lin Y. An Efficient Ensemble Binarized Deep Neural Network on Chip with Perception-Control Integrated. Sensors. 2021; 21(10):3407. https://doi.org/10.3390/s21103407
Chicago/Turabian StyleHe, Wei, Dehang Yang, Haoqi Peng, Songhong Liang, and Yingcheng Lin. 2021. "An Efficient Ensemble Binarized Deep Neural Network on Chip with Perception-Control Integrated" Sensors 21, no. 10: 3407. https://doi.org/10.3390/s21103407