Open AccessArticle

An Improved Second-Order Generalized Integrator Phase-Locked Loop with Frequency Error Compensation

Zhaoyang Yan

^*,

Hanyi Qiao

Zongze Guo

Dongxu Wang

and

Yidan Feng

Key Laboratory of Power Electronics for Energy Conservation and Drive Control of Hebei Province, Yanshan University, Qinhuangdao 066104, China

Author to whom correspondence should be addressed.

Electronics 2025, 14(5), 1018; https://doi.org/10.3390/electronics14051018

Submission received: 17 January 2025 / Revised: 28 February 2025 / Accepted: 1 March 2025 / Published: 3 March 2025

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Abstract

In distributed energy grid-connected systems, fast and accurate grid synchronization technology is crucial for system stability. This article proposes an improved phase-locked loop (FECSOGI-PLL) based on frequency error compensation. By introducing an unbiased adaptive frequency compensation mechanism, the SOGI resonant frequency is adjusted in real time to accurately track the input signal. A linear time invariant (LTI) model of the FECSOGI-PLL was established in the article, and its wider stability domain was clarified based on the Routh–Hurwitz criterion. The strong robustness of its fast response under non-ideal conditions, such as frequency jumps and amplitude drops, was verified through simulation and experiments. The core innovation of this study lies in the first implementation of unbiased adaptive regulation of the SOGI resonant frequency through the frequency error compensation mechanism, as well as the system design method based on the extended stability domain, providing theoretical support and engineering practice reference for high robustness power grid synchronization technology.

Keywords:

frequency error compensation; single-phase; phase-locked loop; second-order generalized integrator; synchronization

1. Introduction

The increasing popularity of distributed generation (DG) units in power systems has led to significant challenges in synchronizing their output voltage with the grid voltage during parallel operation [1]. This is crucial as DG units must operate in harmony with the power grid. To address this, phase-locked loops (PLLs) are widely used in grid-tied inverters to synchronize the output voltage of DG units with the grid in terms of both frequency and phase [2,3]. Consequently, improving the speed and accuracy of PLL phase-locking has become a critical research area.

Recently, numerous approaches to single-phase PLL technologies have emerged. These methods can generally be classified into two categories: power-based phase-locked loops (p-PLLs) and quadrature signal generator phase-locked loops (QSG-PLLs). QSG-PLLs are based on the synchronous reference frame phase-locked loop (SRF-PLL), which has gained popularity due to its superior performance [4]. Most QSG-PLLs incorporate circuits, filters, or algorithms designed to generate virtual orthogonal signals, and their performance heavily depends on the quality of these signals [5]. Various types of QSGs have been proposed, including Park-based QSG [6], SOGI QSG [7], power-based QSG [8], and all-pass filter QSG [9]. Among these, the SOGI-QSG structure is particularly favored due to its simplicity and robustness, making the SOGI-based single-phase PLL a widely used technology for high-performance synchronization in single-phase grid applications [10,11].

Despite its advantages, the SOGI-PLL suffers from several drawbacks, such as harmonic distortion, DC offset issues, and transient response challenges. To enhance the frequency-adaptive capabilities of the SOGI-PLL, researchers have proposed modifications, including a frequency feedback loop that improves phase-locking accuracy under frequency deviations [7]. However, the error between the resonant frequency of the SOGI and the real-time grid frequency can lead to inaccuracies in phase-locking. To address harmonic distortion, a boosted SOGI-PLL (HGI-PLL) has been introduced, which restricts the total harmonic distortion (THD) of the unit vector to within a 1% range under non-ideal conditions [12]. Additionally, to improve transient response, a fixed-parameter SOGI-PLL design has been proposed, ensuring stable performance even during frequency fluctuations [13]. For frequency deviation, Xiao et al. [14] introduced a frequency-fixed SOGI-based PLL (FFSOGI-PLL), which provides accurate synchronization even when frequency drift occurs. However, the earlier methods do not enable the SOGI-PLL to be frequency-adaptive. To address this, an enhanced SOGI-PLL (3CS-SOGI) was proposed by Jin et al. [15], offering improved frequency adaptation and greater stability under weak grid conditions however, it is complex and difficult to implement.

The study by Mohamadian et al. [16] proposes an improved version of the SOGI-PLL that eliminates certain input harmonics and improves phase-locking performance; however, its complexity presents challenges in practical implementation. Zhang et al. [17] highlight the importance of frequency feedback and the accuracy of the SOGI-PLL in maintaining dynamic performance. They provide a method for extracting orthogonal components in a three-phase PLL scenario using the QSG-DSOGI-TSM-PLL model [18]. In this method, the traditional PI controller is replaced by a Terminal Sliding Mode (TSM) controller. The idea of error compensation is similar to this extraction and replacement approach.

Moreover, Xu et al. [19] suggest that nonlinear coupling effects in the phase and frequency estimation loops affect the performance of frequency-adaptive SOGI-PLLs, especially when grid amplitude and frequency fluctuate. As a result, linearizing the PLL structure is necessary to identify stable operating regions and study the nonlinear transient processes involved [20].

This article proposes an improved second-order generalized integrator phase-locked loop (FECSOGI-PLL) based on frequency error compensation to address the problem of dynamic performance degradation of the traditional SOGI-PLL during sudden changes in grid frequency and amplitude. By introducing a frequency error compensation mechanism, unbiased adaptive tracking of the SOGI resonant frequency has been achieved, effectively solving the problem of phase-locking delay and fluctuation caused by the mismatch between the resonant frequency and the real-time frequency of the power grid in traditional methods. A linear time-invariant (LTI) model of the FECSOGI-PLL was established in the article, and its wider stability domain was clarified based on the Routh–Hurwitz criterion. The fast response and strong robustness of the FECSOGI-PLL under non-ideal conditions, such as frequency hopping and amplitude drop, were verified through simulation and experiment. The structure design of the full text is as follows: Section 2 elaborates on the working principle and compensation mechanism design of the FECSOGI-PLL. The third section quantitatively reveals its performance advantages through theoretical modeling and stability analysis. The fourth section combines simulation verification to improve dynamic performance. Section 5: Engineering practicality of the method supported by multi-condition experimental data; summarize the final results and look forward to future research directions.

2. Description of the Proposed FECSOGI-PLL

2.1. The Working Principle of SOGI-PLL

Figure 1 presents the algorithm principle block diagram of the SOGI-QSG.

The transfer functions of the SOGI are given by Equations (1) and (2):

G_{α} (s) = \frac{{\hat{v}}_{α}}{v} (s) = \frac{k {\hat{ω}}_{s} s}{s^{2} + k {\hat{ω}}_{s} s + {\hat{ω}}_{s}^{2}}

(1)

G_{β} (s) = \frac{{\hat{v}}_{β}}{v} (s) = \frac{k {\hat{ω}}_{s}^{2}}{s^{2} + k {\hat{ω}}_{s} s + {\hat{ω}}_{s}^{2}}

(2)

In (1) and (2),

k

is the damping ratio;

{\hat{ω}}_{s}

is the filter center angle frequency;

G_{α} (s)

is the transfer function of the band-pass filter;

G_{β} (s)

is the transfer function of the low-pass filter.

Obtaining tracking of the angular frequency of the signal is accomplished by the filter when the resonant frequency of the filter is equal to the angular frequency of the signal that is being input.

When the values

k

are different, the Bode diagrams

G_{α} (s)

and

G_{β} (s)

are shown in Figure 2. By adjusting

k

, it is possible to regulate the bandwidth of the filter. Decreasing the value of

k

can lead to better filtering effects, but it will slow down the dynamic response; increasing the value of

k

can quicken the system’s response speed, but it will reduce the system’s ability to resist interference from harmonics in the input signal. Built upon a compromise considering the above situations,

k = 1.414

is chosen such that the system balances response speed and robustness.

Figure 3 presents the single-phase PLL based on the SOGI-PLL structure. The SOGI-PLL employs the SOGI-QSG to construct virtual orthogonal signals and leverages its low-pass and band-pass characteristics to cancel high-order harmonics, thereby extracting the fundamental sequence component of the grid voltage to complete phase-locking.

It should be noted that when the resonant frequency of the SOGI

{\hat{ω}}_{s}

differs from the frequency of the input signal

ω_{n}

, there will be tracking errors in both the amplitude and phase of the SOGI output signal. This causes a huge decrease in the rapidity and robustness of the SOGI-PLL locking process, especially under non-ideal conditions where the input signal experiences sudden changes in frequency and amplitude.

2.2. The Working Principle of the FECSOGI-PLL

In response to the degradation of dynamic performance in the traditional SOGI-PLL during frequency and amplitude sudden changes, a frequency error compensation link has been proposed. This enables the resonant frequency of the SOGI to be adaptively adjusted without bias to match the frequency of the input signal. It solves the problem caused by the phase-locked loop’s tracking error, where the SOGI’s resonant frequency cannot adapt bias-free to the input frequency, thus failing to accurately and stably lock onto the input signal. Consequently, this enhancement improves the rapidity and robustness of the SOGI-PLL, namely the FECSOGI-PLL, and its structure block diagram is presented in Figure 4.

The design of the compensation link is as follows:

\{\begin{cases} ω_{e} = ω_{n} - {\hat{ω}}_{p l l} \\ {\hat{ω}}_{s} = {\hat{ω}}_{p l l} + ω_{e} \end{cases}

(3)

The frequency obtained through the phase-locked loop is

{\hat{ω}}_{p l l}

; the frequency of the input signal is

ω_{n}

; the resonant frequency of the SOGI is denoted as

{\hat{ω}}_{s}

; the error between the frequency obtained from the PLL and the input frequency is

ω_{e}

\begin{array}{l} {\hat{ω}}_{s} & = {\hat{ω}}_{p l l} + ω_{e} \\ = {\hat{ω}}_{p l l} + ω_{n} - {\hat{ω}}_{p l l} \\ = ω_{n} \end{array}

(4)

From Equation (4), it can be deduced that the output frequency derived from the input signal via the FECSOGI-PLL, after the error compensation structure introduced in this article, is adaptively adjusted to correspond with the input signal frequency. This ensures that the resonant frequency

{\hat{ω}}_{s}

of the SOGI is perpetually tuned to the input signal frequency

ω_{n}

. Consequently, the SOGI-PLL becomes more efficient in its dynamic operation, particularly in the face of transient challenges.

From Figure 5, it is evident that a sudden change in the grid frequency occurs at 0.25 s. In the traditional SOGI-PLL, the resonant frequency

{\hat{ω}}_{s}

fed back to the SOGI cannot quickly track the grid input frequency

ω_{n}

, which causes the inability of the traditional SOGI-PLL to rapidly and precisely lock onto the grid phase. Unlike, in the FECSOGI-PLL, the addition of a frequency error compensation link allows the error between the resonant frequency

{\hat{ω}}_{s}

fed back to the SOGI and the input frequency to be compensated. This enables the resonant frequency

{\hat{ω}}_{s}

to directly track the input frequency

ω_{n}

, thereby significantly enhancing the rapidity of the phase-locked loop.

3. Modeling and Analysis of the FECSOGI-PLL

To further illustrate that the FECSOGI-PLL suggested in this study has upgraded rapidity and stability in contrast to the traditional SOGI-PLL, this section conducts stability analysis and parameter selection for the FECSOGI-PLL by establishing a Linear Time-Invariant (LTI) model [18].

In the modeling process, the single-phase input signal is set as

v (t) = V \cos (θ)

(5)

Based on the phase and frequency characteristics of the SOGI discussed in the previous section, the output signals

{\hat{v}}_{α} (t)

and

{\hat{v}}_{β} (t)

of the SOGI can be defined as:

\{\begin{cases} {\hat{v}}_{α} (t) = \hat{V} \cos ({\hat{θ}}_{1}) \\ {\hat{v}}_{β} (t) = \hat{V} \sin ({\hat{θ}}_{1}) \end{cases}

(6)

where

\hat{V}

is the estimated value of

V

;

{\hat{θ}}_{1}

refers to the calculated value from the SOGI output signals.

Assuming that the SOGI-PLL operates in a stable state, then

\hat{V} \approx V

{\hat{ω}}_{s} \approx {\hat{ω}}_{n}

, and

{\hat{θ}}_{2} \approx {\hat{θ}}_{1} \approx θ

. According to Figure 4, the expressions for the angular frequency, phase angle, and amplitude estimates obtained from the SOGI-PLL are:

\{\begin{cases} {\hat{ω}}_{p l l} = k_{p} V_{q} + \int k_{i} V_{q} d t + ω_{n} \\ {\hat{θ}}_{1} = \tan^{- 1} ({\hat{v}}_{β} / {\hat{v}}_{α}), {\hat{θ}}_{2} = \int {\hat{ω}}_{p l l} d t \\ \hat{V} = \sqrt{v_{α}^{2} + v_{β}^{2}} \end{cases}

(7)

The q-axis output voltage obtained through the Park transformation is expressed as:

V_{q} = - {\hat{v}}_{α} \sin ({\hat{θ}}_{2}) + {\hat{v}}_{β} \cos ({\hat{θ}}_{2}) = \hat{V} \sin ({\hat{θ}}_{1} - {\hat{θ}}_{2})

(8)

Equation (7) allows us to derive the time-dependent derivatives of the phase angle and amplitude as:

\{\begin{cases} \frac{d {\hat{θ}}_{1}}{d t} = \frac{d [\tan^{- 1} ({\hat{v}}_{β} / {\hat{v}}_{α})]}{d t} = \frac{1}{{\hat{V}}^{2}} ({\hat{v}}_{α} \frac{d {\hat{v}}_{β}}{d t} - {\hat{v}}_{β} \frac{d {\hat{v}}_{α}}{d t}) \\ \frac{d {\hat{θ}}_{2}}{d t} = {\hat{ω}}_{p l l} \\ \frac{d \hat{V}}{d t} = \frac{d \sqrt{{\hat{v}}_{α}^{2} + {\hat{v}}_{β}^{2}}}{d t} = \frac{1}{\hat{V}} ({\hat{v}}_{α} \frac{d {\hat{v}}_{α}}{d t} + v_{β} \frac{d {\hat{v}}_{β}}{d t}) \end{cases}

(9)

In Equation (9),

\frac{d {\hat{v}}_{α}}{d t}

and

\frac{d {\hat{v}}_{β}}{d t}

can be derived from Figure 1:

\{\begin{cases} \frac{d {\hat{v}}_{α}}{d t} = - {\hat{ω}}_{s} {\hat{v}}_{β} + (v - {\hat{v}}_{α}) k {\hat{ω}}_{s} \\ \frac{d {\hat{v}}_{β}}{d t} = {\hat{ω}}_{s} {\hat{v}}_{α} \end{cases}

(10)

Substituting Equations (7), (8), and (10) into Equation (9) yields:

\{\begin{cases} \frac{d {\hat{θ}}_{1}}{d t} = {\hat{ω}}_{s} - \frac{1}{{\hat{v}}_{2}} {\hat{v}}_{β} (v - {\hat{v}}_{α}) k {\hat{ω}}_{s} \\ \frac{d {\hat{θ}}_{2}}{d t} = k_{p} \hat{V} \sin ({\hat{θ}}_{1} - {\hat{θ}}_{2}) + \\ \int k_{i} \hat{V} \sin ({\hat{θ}}_{1} - {\hat{θ}}_{2}) d t + ω_{n} \\ \frac{d \hat{V}}{d t} = \frac{1}{\hat{V}} \{k [{\hat{v}}_{α} (v - {\hat{v}}_{α}) {\hat{ω}}_{s}]\} \end{cases}

(11)

It is the nonlinear control differential equation of the FECSOGI-PLL that is represented by Equation (11). Linearization of the equation is performed in accordance with the theory of linear time-invariant (LTI) systems in order to obtain the linear model of the FECSOGI-PLL structure.

Under normal circumstances, actual variables and estimated variables exhibit rated values and small signal perturbation values in a way that is equivalent to:

\{\begin{cases} V = V_{n} + Δ V, \hat{V} = V_{n} + Δ \hat{V} \\ θ = θ_{n} + Δ θ, {\hat{θ}}_{1} = θ_{n} + Δ {\hat{θ}}_{1}, θ_{2} = θ_{n} + Δ {\hat{θ}}_{2} \\ ω = ω_{n} + Δ ω, {\hat{ω}}_{p l l} = ω_{n} + Δ {\hat{ω}}_{p l l} \end{cases}

(12)

In the equations,

Δ

and

n

respectively denote small perturbations and rated values. In this paper,

V_{n} = 311 V

ω_{n} = 50 * 2 π r α d / s

, and

θ_{n} = \int ω_{n} d t = ω_{n} t

represent the small perturbations in frequency, voltage, and phase, respectively.

Substituting Equation (6) into Equation (11) results in Equation (13).

\{\begin{cases} \frac{d {\hat{θ}}_{1}}{d t} = {\hat{ω}}_{s} - k {\hat{ω}}_{s} [\cos (\hat{θ}) - \cos ({\hat{θ}}_{1})] \sin ({\hat{θ}}_{1}) \\ \approx {\hat{ω}}_{s} + \frac{k}{2} {\hat{ω}}_{s} (θ - {\hat{θ}}_{1}) \\ \frac{d {\hat{θ}}_{2}}{d t} = k_{p} V \sin ({\hat{θ}}_{1} - {\hat{θ}}_{2}) + \\ \int k_{i} V \sin ({\hat{θ}}_{1} - {\hat{θ}}_{2}) dt + ω_{n} \end{cases}

(13)

Substituting Equation (12) into Equation (13), the LTI model of the FECSOGI-PLL is able to be derived as Equation (14), with the block diagram presented in Figure 6a.

\{\begin{cases} \frac{d Δ {\hat{θ}}_{1}}{d t} \approx ω_{n} + \frac{k}{2} ω_{n} (Δ θ - Δ {\hat{θ}}_{1}) \\ \approx ω_{n} + Z (Δ θ - Δ {\hat{θ}}_{1}) \\ \frac{d Δ {\hat{θ}}_{2}}{d t} \approx k_{p} (V_{n} + Δ V) (Δ {\hat{θ}}_{1} - Δ {\hat{θ}}_{2}) \\ + (V_{n} + Δ V) \int k_{i} (Δ {\hat{θ}}_{1} - Δ {\hat{θ}}_{2}) d t \end{cases}

(14)

According to the established LTI model, the transfer function of the FECSOGI-PLL’s LTI model (Model A) could be acquired by Equation (16). The LTI model of the SOGI-PLL (Model B) is presented in Figure 6b [21], and its transfer function is given in Equation (15) [21]. The Routh–-Hurwitz calculation table is shown in Table 1

G_{s o g i}^{L T I} = \frac{Δ {\hat{θ}}_{2} (s)}{Δ θ (s)} = \frac{Z V_{n} k_{p} s + Z V_{n} k_{i}}{s^{3} + Z s^{2} + Z V_{n} k_{p} s + Z V_{n} k_{i}}

(15)

G_{f e c s o g i}^{L T I} = \frac{Δ {\hat{θ}}_{2} (s)}{Δ θ (s)} = \frac{Z V_{n} k_{p} s + Z V_{n} k_{i}}{s^{3} + (V_{n} k_{p} + Z) s^{2} + (V_{n} k_{i} + Z V_{n} k_{p}) s + Z V_{n} k_{i}}

(16)

In accordance with the Routh–Hurwitz stability criterion, the stability region for Model A can be determined as:

\{\begin{cases} k_{i} > 0 \\ k_{p} > 0 \end{cases}

(17)

The stability region of the SOGI-PLL’s LTI model, as referenced in Wang et al. [20]:

\{\begin{cases} Z k_{p} - k_{i} > 0 \\ Z k_{p} > k_{i} \end{cases}

(18)

By comparing Equations (17) and (18), it is found that Model A of the FECSOGI-PLL can remain in a steady state when the conditions for

k_{p} > 0

and

k_{i} > 0

are met, and its stability region is much larger than that of the SOGI-PLL.

From Figure 6b, the open-loop transfer function and the closed-loop error transfer function of Model A can be obtained as Equations (19) and (20).

H (s) = \frac{s^{3}}{s^{3} + (Z + ω_{n}) V_{n} k_{p} s + (Z + ω_{n}) V_{n} k_{i}}

(19)

G_{e} (s) = \frac{1}{1 + H (s)} = \frac{s^{3}}{s^{3} + (Z + ω_{n}) V_{n} k_{p} s + (Z + ω_{n}) V_{n} k_{i}}

(20)

After obtaining the closed-loop error transfer function, a steady-state error analysis is performed for a frequency step input. The expression for the frequency step is given as:

\hat{θ} (s) = \frac{Δ \hat{ω}}{s^{2}}

(21)

Using the frequency step signal and the closed-loop error transfer function, the error expression can be derived as:

\begin{array}{r} e (s) = \hat{θ} (s) G_{e} (s) = \frac{Δ \hat{ω}}{s^{2}} \cdot \frac{s^{3}}{s^{3} + (Z + ω_{n}) V_{n} k_{p} s + (Z + ω_{n}) V_{n} k_{i}} \\ = \frac{Δ \hat{ω} s}{s^{3} + (Z + ω_{n}) V_{n} k_{p} s + (Z + ω_{n}) V_{n} k_{i}} \end{array}

(22)

The steady-state error of the system is:

\lim_{s \to \infty} s \cdot e (s) = \lim_{s \to \infty} \frac{Δ \hat{ω} s}{s^{3} + (Z + ω_{n}) V_{n} k_{p} s + (Z + ω_{n}) V_{n} k_{i}} = 0

(23)

According to Equation (23), the system’s steady-state error is zero when given a frequency step as an input.

To further determine the controller parameters, assume that the grid voltage amplitude (V) is 1 V. The selection criteria include achieving a phase margin of 45° and a bandwidth of 40 Hz. Using these specifications, the PI parameters obtained from (24) are substituted into (19).

\{\begin{matrix} |H (j 40 * 2 π)| = 1 \\ 180^{\circ} + ∠ H (j 40 * 2 π) {= 45}^{\circ} \end{matrix}

(24)

The parameters obtained after the calculation are as follows:

\{\begin{matrix} K_{P} = 163 \\ K_{i} = 36,203.93 \end{matrix}

(25)

4. Simulation Verification

Assuming the input signal voltage amplitude is 311 V and the frequency is 50 Hz, that is,

V_{n} = 311 V

and

ω_{n} = 50 * 2 π

, substituting these assumed conditions into Equation (18) yields Equation (26):

k_{i} < 222.11 k_{p}

(26)

That is, when

k_{p}

and

k_{i}

satisfy Equation (19), Model B is in a stable state. According to Xu et al. [18], with

k_{p} = 100

, it is calculated from Equation (26) that the SOGI-PLL is in a stable state when

k_{i} < 22,210

. To further verify that the robustness of the FECSOGI-PLL is more effective than that of the SOGI-PLL, two sets of the same parameters are taken both inside and outside the stability domain of Model B for comparative simulation verification of Models A and B, with the input value being 1. Table 2 displays the specific parameters.

As shown in Figure 7a, both Model A and Model B can stably output 1 under the conditions of Case 1 (

k_{p} = 100, k_{i} = 22,210

), and both systems are in a stable state, which is consistent with the system stability conditions mentioned earlier. According to Figure 7b, under the conditions of Case 2 (

k_{p} = 100, k_{i} = 22,212

), Model A can still maintain a stable output of 1, but Model B is not stable, which aligns with the stability conditions calculated earlier.

In conclusion, based on Equations (17) and (18) as well as Figure 8, it can be proven that the stability region of Model A is significantly greater than Model B, thereby verifying that the stability of the FECSOGI-PLL is better than the traditional SOGI-PLL.

In order to validate even more thoroughly the stability and dynamic performance of the proposed FECSOGI-PLL, a comparative transient response simulation is conducted between the FECSOGI-PLL and the SOGI-PLL under the same parameter conditions. A frequency disturbance

Δ f = 5 Hz

is applied to the system at 0.25 s, and a dual disturbance of frequency and amplitude

Δ f = 5 Hz

and

Δ V = 100 V

is applied at the same time, respectively. The PI parameter selection for the FECSOGI-PLL and SOGI-PLL is shown in Table 3. The DQ-axis output curves of the FECSOGI-PLL and SOGI-PLL are presented in Figure 8.

Figure 8a clearly shows that, due to the addition of the error compensation link, when the input voltage frequency changes abruptly, the FECSOGI-PLL, in comparison with the traditional SOGI-PLL, can instantly lock onto the frequency after the change. The fluctuation of the Q-axis at the frequency jump is significantly reduced and quickly and stably tracks to 0. At the same time, the D-axis can track the input voltage within 0.03 s. Therefore, based on the working principle of the phase-locked loop, the FECSOGI-PLL can still quickly lock onto the information of the input voltage when a sudden change happens in the input frequency. Figure 8b clearly shows that when a simultaneous sudden variation happens in both the input voltage amplitude and frequency, compared to the traditional SOGI-PLL, the FECSOGI-PLL, due to the addition of the error compensation link, can quickly and stably lock onto the input voltage’s amplitude and frequency. The Q-axis can still quickly and stably track to 0, and the D-axis can also track the input voltage in a short period. This allows the phase-locked loop to quickly lock onto the input voltage, showing the good rapidity and robustness of the proposed error compensation method.

In summary, the incorporation of the error compensation link in the traditional SOGI-PLL has enabled the FECSOGI-PLL to more rapidly and stably track the input voltage in response to transient changes in input voltage frequency and amplitude. This significantly enhances the rapidity and robustness of the traditional SOGI-PLL.

5. Experimental Results and Discussions

In order to more thoroughly substantiate the enhanced rapid response and robustness of the FECSOGI-PLL in comparison to the conventional SOGI-PLL, as well as to confirm the viability and efficacy of the approaches that have been proposed, a comparative experimental validation has been carried out between the FECSOGI-PLL and the traditional SOGI-PLL.

The experiment was conducted using a simulation of a grid-tied system, where the single-phase voltage was virtually generated by a Digital Signal Processor (DSP), acting as a virtual power grid. After being sampled by an A/D conversion board, the signal was input to the DSP for grid synchronization, ultimately achieving synchronization with the power grid. The experimental platform diagram is shown in Figure 9.

The experimental system specifications are provided in Table 4.

The experiments are divided into the following two scenarios, as shown in Table 5:

Figure 10 compares the output waveforms of the SOGI-PLL and FECSOGI-PLL under grid frequency transient conditions. Both the grid input voltage and the phase angle output waveforms of the two phase-locked loops are depicted in Figure 10a. A representation of the DQ-axis output waveforms of the two phase-locked loops can be found in Figure 10b.

From Figure 10a, it is evident that after a frequency jump occurs, unlike the traditional SOGI-PLL, the resonant frequency of the SOGI can quickly adapt to the grid input frequency due to the error compensation link proposed in this paper. This allows the phase angle of the FECSOGI-PLL to quickly and stably track the grid phase and reach a steady state within one grid cycle. In contrast, the output phase angle of the SOGI-PLL has deviations because after a frequency jump, the resonant frequency of the SOGI-PLL and the grid’s real-time frequency have a discrepancy, which prevents the Q-axis from quickly stabilizing at zero, resulting in significant fluctuations. This leads to the inability of the SOGI-PLL to accurately lock onto the grid phase information, as shown in Figure 11b. Figure 10b makes it crystal clear that after a frequency jump, due to the addition of the error compensation link, the D-axis of the FECSOGI-PLL is steady within 0.025 s, locking onto the grid voltage, and its Q-axis approaches zero and reaches a steady state within 0.025 s. However, the traditional SOGI-PLL, when faced with a frequency jump, shows a clear dynamic response process in both DQ axes, with significant output fluctuations, and the Q-axis cannot quickly approach zero, leading to the inability of the SOGI-PLL to quickly lock onto the grid phase information. In comparison, with the addition of the error compensation link, the resonant frequency of SOGI can adapt to the real-time grid frequency, enabling the FECSOGI-PLL to quickly and stably lock onto the grid phase information even under transient changes caused by grid frequency jumps. This validates the rapidity and stability of the approach suggested in this paper.

As shown in Figure 10c, the FECSOGI-PLL demonstrates significant superiority under frequency jump conditions. Compared to the other three phase-locked loops (SOGI-PLL, APF-PLL, FFSOGI-PLL), FECSOGI-PLL exhibits the fastest frequency recovery, the smallest overshoot, and almost zero steady-state error. The waveform smoothly and rapidly recovers to the target frequency, indicating its strong dynamic response to frequency jumps. The SOGI-PLL shows considerable overshoot and longer recovery time, with poor frequency output stability, highlighting its limitations in handling frequency jumps. Although the APF-PLL responds relatively quickly, its frequency output still experiences significant overshoot, and the steady-state error is large, with a relatively slow recovery process. The FFSOGI-PLL shows improvement compared to the SOGI-PLL and APF-PLL but still falls short of the FECSOGI-PLL, with some frequency deviation and smaller overshoot. The recovery smoothness and precision still need improvement. Overall, the FECSOGI-PLL exhibits the strongest performance in recovery speed, steady-state accuracy, and overshoot control. Particularly in the face of frequency jump conditions, it provides the most accurate and rapid frequency output, significantly outperforming the other three phase-locked loops.

Figure 11a illustrates that when both the grid frequency and amplitude experience abrupt alterations, the output phase angle waveform of the conventional SOGI-PLL displays discrepancies and is unable to promptly synchronize with the grid phase information. Conversely, the FECSOGI-PLL, by integrating a frequency error compensation link, enables the resonant frequency of the SOGI to adjust in real time to the grid input frequency. Thus, the FECSOGI-PLL can swiftly synchronize with the grid phase information within a single grid cycle and attain a steady state, underscoring the efficiency of the method presented in this paper. Figure 11b clearly demonstrates that following a transient alteration in the grid, the DQ-axis output of the conventional SOGI-PLL exhibits fluctuations, hindering the prompt and stable acquisition of the grid phase information. Nonetheless, the FECSOGI-PLL, incorporating the frequency error compensation link, facilitates the rapid locking of the D-axis onto the grid amplitude information and achieves stabilization, while the Q-axis also swiftly approaches zero and attains a steady state. This enables the FECSOGI-PLL to swiftly and reliably synchronize with the grid phase information, even amidst grid fluctuations. In comparison, the FECSOGI-PLL can quickly and stably lock onto the grid phase information when both the grid amplitude and frequency change simultaneously, further validating the applicability and effectiveness of the method suggested by this study.

As shown in Figure 10c, the FECSOGI-PLL demonstrates significant superiority under frequency jump conditions. Compared to the other three phase-locked loops (SOGI-PLL, APF-PLL, FFSOGI-PLL), FECSOGI-PLL exhibits the fastest frequency recovery, the smallest overshoot, and almost zero steady-state error. The waveform smoothly and rapidly recovers to the target frequency, indicating its strong dynamic response to frequency jumps. The SOGI-PLL shows considerable overshoot and longer recovery time, with poor frequency output stability, highlighting its limitations in handling frequency jumps. Although the APF-PLL responds relatively quickly, its frequency output still experiences significant overshoot, and the steady-state error is large, with a relatively slow recovery process. The FFSOGI-PLL shows some improvement compared to the SOGI-PLL and APF-PLL but still falls short when compared to the FECSOGI-PLL, with some frequency deviation and smaller overshoot. The smoothness and accuracy of recovery still need improvement. Overall, FECSOGI-PLL exhibits the strongest performance in recovery speed, steady-state accuracy, and overshoot control. Particularly in the face of frequency jump conditions, it provides the most accurate and rapid frequency output, significantly outperforming the other three phase-locked loops.

As shown in Figure 12a, the FECSOGI-PLL demonstrates significant superiority under DC bias and frequency jump conditions. During a frequency jump, the frequency output waveform of the FECSOGI-PLL shows almost no overshoot, and its recovery to steady-state is very fast with minimal steady-state error, indicating its strong frequency stability and dynamic response capability. In contrast, the SOGI-PLL shows significant overshoot during the recovery after the frequency jump, with a longer recovery time and larger steady-state error, highlighting its shortcomings in dynamic response. Although the APF-PLL shows improved response speed, it still experiences overshoot during recovery after the frequency jump, with a relatively large steady-state error. The FFSOGI-PLL shows better dynamic response but still falls short of the FECSOGI-PLL, with some frequency deviation and delayed recovery time. Therefore, the FECSOGI-PLL not only recovers quickly to the target frequency under frequency jumps and DC bias but also maintains the smallest steady-state error, exhibiting the best performance.

Figure 12b shows that the FECSOGI-PLL still demonstrates its significant advantages in frequency stability and dynamic response. Despite smaller disturbances, the FECSOGI-PLL can quickly and smoothly return to steady-state with almost no overshoot, and the steady-state error is nearly zero, showing extremely high precision and superior stability. In comparison, the SOGI-PLL exhibits larger overshoot and fluctuations during recovery, with larger steady-state error, indicating its poor suppression of small disturbances. The APF-PLL has a slower recovery speed and experiences some overshoot, with larger steady-state error, failing to achieve the precision of the FECSOGI-PLL. Although the FFSOGI-PLL shows some improvement over the other phase-locked loops, it still has some steady-state error and overshoot, not achieving the optimal control effect of the FECSOGI-PLL. Therefore, even under small disturbance conditions, the FECSOGI-PLL still demonstrates the strongest dynamic response and stability, effectively suppressing frequency deviation and returning to steady-state, showing its excellent performance in precise frequency control and rapid response.

To further compare the phase-locking performance of the four phase-locked loops, we conducted a performance evaluation of four different types of phase-locked loops (APF-PLL, FFSOGI-PLL, SOGI-PLL, FECSOGI-PLL), focusing on their dynamic response and stability under different conditions. The experimental data include several key performance metrics, including IAE (Integral Absolute Error), ITAE (Integral Time Absolute Error), and ISV (Instantaneous Error Variation), which comprehensively evaluate the performance of each phase-locked loop from the perspectives of error size, response speed, and system stability. Through an in-depth analysis of the experimental data, we can visually compare the advantages and disadvantages of each phase-locked loop and identify the outstanding performance of the FECSOGI-PLL, especially under complex conditions like frequency jumps. The detailed analysis of the experimental data is shown in Table 6.

Through experimental data analysis of four phase-locked loops (APF-PLL, FFSOGI-PLL, SOGI-PLL, FECSOGI-PLL) based on IAE, ITAE, and ISV metrics, several key conclusions can be drawn. First, IAE (Integral Absolute Error), an important indicator for measuring the overall system error, shows that the FECSOGI-PLL performs the best under frequency jumps, with a value of 3.35, significantly lower than the other three methods (APF-PLL: 56.7, FFSOGI-PLL: 17.8, SOGI-PLL: 136.06). This result indicates that the FECSOGI-PLL effectively reduces errors during large frequency variations, demonstrating significantly higher precision than other types of phase-locked loops. Second, ITAE (Integral Time Absolute Error) not only considers the size of the error but also the duration of the error. A smaller ITAE value means the system can return to a stable state in a shorter time. The FECSOGI-PLL also performs well in this metric, with an ITAE of 16.57 under frequency jumps, much lower than other methods. This demonstrates that the FECSOGI-PLL not only reduces errors quickly but also recovers to a stable state promptly, indicating strong dynamic response capabilities. Finally, ISV (Instantaneous Error Variation) reflects the stability of the system in terms of instantaneous error fluctuations. The FECSOGI-PLL has the lowest ISV value of 0.13 among the four methods, indicating the lowest instantaneous error fluctuation under frequency jumps and superior system stability. In summary, the FECSOGI-PLL excels in all evaluation metrics, particularly under non-ideal conditions like frequency jumps, showing more accurate, faster, and stable performance. Therefore, the FECSOGI-PLL offers clear technical advantages in applications requiring high precision and stability.

6. Conclusions

This paper proposes an improved second-order generalized integrator phase-locked loop (FECSOGI-PLL) based on frequency error compensation. By introducing a frequency error compensation mechanism, it achieves unbiased adaptive tuning of the SOGI resonant frequency, effectively addressing the dynamic performance degradation issue of the traditional SOGI-PLL under sudden grid frequency and amplitude fluctuations. The core contributions include the design of a simple frequency compensation structure, the establishment of a linear time-invariant model, and verification of its broader stability region. Simulation and experimental results demonstrate its performance advantages, such as fast phase-locking within 0.025 s and reduced DQ-axis fluctuations. However, the robustness of the FECSOGI-PLL under high-frequency noise and complex harmonic interference scenarios still needs further validation. The FECSOGI-PLL has broad application prospects in fields such as distributed generation grid connection and photovoltaic inverter synchronization, particularly in smart grid scenarios that require rapid frequency tracking and amplitude control. Future work could focus on optimizing compensation parameters by integrating intelligent algorithms, such as fuzzy control or sliding mode control, to enhance the system’s disturbance rejection capability.

Author Contributions

Conceptualization, Z.Y.; writing—original draft preparation, H.Q.; writing—review and editing, Z.Y. and H.Q.; software, Z.G.; formal analysis, Y.F.; funding acquisition, Z.Y.; investigation, D.W. All authors have read and agreed to the published version of the manuscript.

Funding

This work was funded by the National Natural Science Foundation of China (Grant No. 61671403), the National Key Research and Development Program of China (Grant No. 2016YFC0802900), and the Hebei Provincial Natural Science Foundation Innovation Research Group Continuation Funding Project (Grant No. E2024203257).

Data Availability Statement

The authors will provide the raw data supporting the conclusions of this article upon request.

Conflicts of Interest

The authors assert the absence of any conflicts of interest.

Abbreviations

The following abbreviations are employed in the study:

SOGI	Second-Order Generalized Integrator
PLL	Phase-Locked Loop
FECSOGI-PLL	Frequency Error Compensation SOGI-PLL
LTI	Linear Time-Invariant
DG	Distributed Generation
p-PLL	Power-Based Phase-Locked Loop
QSG-PLL	Quadrature Signal Generator Phase-Locked Loop
SRF-PLL	Synchronous Reference Frame Phase-Locked Loop
HGI-PLL	Harmonic Distortion Issues an Improved SOGI-PLL
THD	Total Harmonic Distortion
DSP	Digital Signal Processor
IAE	Absolute Error
ITAE	Integral Time Absolute Error
ISV	Integral Squared Error

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Figure 1. SOGI-QSG structure diagram.

Figure 2. The relationship between the Bode plots of

G_{α} (s)

and

G_{β} (s)

with the variation of system gain. (a) The Bode plot of

G_{α} (s)

. (b) The Bode plot of

G_{β} (s)

Figure 2. The relationship between the Bode plots of

G_{α} (s)

and

G_{β} (s)

with the variation of system gain. (a) The Bode plot of

G_{α} (s)

. (b) The Bode plot of

G_{β} (s)

Figure 3. SOGI-PLL structure block diagram.

Figure 4. Structure block diagram of FECSOGI-PLL.

Figure 5. Waveform diagram of the feedback SOGI resonant frequency

{\hat{ω}}_{s}

Figure 5. Waveform diagram of the feedback SOGI resonant frequency

{\hat{ω}}_{s}

Figure 6. LTI model block diagrams of FECSOGI-PLL and SOGI-PLL, where

Z = \frac{k ω_{n}}{2}

P = k_{p} V_{n} + \frac{k_{i} V_{n}}{s}

. (a) The LTI model of the FECSOGI-PLL. (b) The LTI model of the SOGI-PLL.

Figure 6. LTI model block diagrams of FECSOGI-PLL and SOGI-PLL, where

Z = \frac{k ω_{n}}{2}

P = k_{p} V_{n} + \frac{k_{i} V_{n}}{s}

. (a) The LTI model of the FECSOGI-PLL. (b) The LTI model of the SOGI-PLL.

Figure 7. Comparison of LTI model outputs between the two under the same

k_{p}

and

k_{i}

conditions. (a) Case 1. (b) Case 2.

Figure 7. Comparison of LTI model outputs between the two under the same

k_{p}

and

k_{i}

conditions. (a) Case 1. (b) Case 2.

Figure 8. Waveforms of DQ-axis outputs for SOGI-PLL and FECSOGI-PLL under input voltage frequency step changes. (a) DQ-axis output waveforms under input voltage frequency step changes. (b) DQ-axis output waveforms under simultaneous input amplitude and frequency step changes.

Figure 9. Experiential setup.

Figure 10. Power grid frequency mutation. (a) Output phase angle of the SOGI-PLL and FECSOGI-PLL. (b) DQ-axis output of the SOGI-PLL and FECSOGI-PLL. (c) Frequency output waveforms of SOGI-PLL, FECSOGI-PLL, APF-PLL, FFSOGI-PLL.

Figure 11. Simultaneous mutation of power grid frequency and amplitude. (a) Output phase angle of the SOGI-PLL and FECSOGI-PLL. (b) DQ-axis output of the SOGI-PLL and FECSOGI-PLL. (c) Frequency output waveforms of SOGI-PLL, FECSOGI-PLL, APF-PLL, FFSOGI-PLL.

Figure 12. (a) Frequency output waveforms of SOGI-PLL, FECSOGI-PRL, APF-PLL, and FFSOGI-PRL under small frequency disturbances. (b) Frequency output waveforms of SOGI-PLL, FECSOGI-PLL, APF-PLL, and FFSOGI-PLL under the frequency jump of adding DC bias.

Table 1. Routh–Hurwitz calculation table.

$s^{3}$	$1$	$k_{i} V_{n} + Z k_{p} V_{n}$
$s^{2}$	$k_{p} V_{n} + Z$	$k_{i} V_{n} Z$
$s^{1}$	$\frac{(k_{p} V_{n} + Z) (k_{i} V_{n} + k_{p} V_{n} Z) - k_{i} V_{n} Z}{k_{p} V_{n} + Z}$	$0$
$s^{0}$	$k_{i} Z$	$0$

Table 2. The simulation parameters for the small-signal model.

Model	Value
SOGI-PLL	$c a s e 1 : \{\begin{cases} k_{p} = 100 \\ k_{i} = 22,210 \end{cases}$
FECSOGI-PLL	$c a s e 2 : \{\begin{cases} k_{p} = 100 \\ k_{i} = 22,212 \end{cases}$

Table 3. Control parameters.

Model	Value
SOGI-PLL [21]	$k_{p} = 137.5$	$k_{i} = 7878$
FECSOGI-PLL	$k_{p} = 163$	$k_{i} = 36,203$

Table 4. System specifications.

Device	Specifications
DSP	TMS320F28335
Emulator	XDS100V3
Auxiliary power supply	±15 v, 5 v
DA chip	TLV5620IDR
AD chip	TLC272IDR

Table 5. Experimental description.

Experimental Conditions	Input Variable	Transient Change
Frequency jump	$V = 1 V$ $f = 50 Hz$	$Δ f = 5 %$
Frequency jump and amplitude drop	$V = 1 V$ $f = 50 Hz$	$Δ f = 5 %$ $Δ V = 10 %$
Small frequency disturbance	$V = 1 V$ $f = 50 Hz$	$Δ f = 1 %$
DC bias and frequency jump	$V = 1 V$ $f = 50 Hz$	$Δ f = 5 %$ $V_{d c} = 0.5 V$

Table 6. Evaluation index data.

Experimental Conditions/Performance Indicators	Model/Parameter Values
DC Bias with Frequency Jump	APF-PLL	FFSOGI-PLL	SOGI-PLL	FECSOGI-PLL
IAE	6.04	4.19	13.76	3.32
ITAE	30.13	20.95	68.66	16.57
ISV	0.19	0.16	0.81	0.13
Frequency jump	APF-PLL	FFSOGI-PLL	SOGI-PLL	FECSOGI-PLL
IAE	56.7	17.8	136.06	3.35
ITAE	277.06	87.15	665.35	16.41
ISV	1.13	0.71	7.48	0.13
Small disturbance	APF-PLL	FFSOGI-PLL	SOGI-PLL	FECSOGI-PLL
IAE	14.5	6.31	12.73	5.02
ITAE	16.43	7.16	14.43	5.69
ISV	0.45	0.13	0.36	0.09
Frequency jump and amplitude drop	APF-PLL	FFSOGI-PLL	SOGI-PLL	FECSOGI-PLL
IAE	367.74	8.08	231.74	3.67
ITAE	1784.95	39.05	1124.5	17.82
ISV	37.5	0.32	15.31	0.14

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MDPI and ACS Style

Yan, Z.; Qiao, H.; Guo, Z.; Wang, D.; Feng, Y. An Improved Second-Order Generalized Integrator Phase-Locked Loop with Frequency Error Compensation. Electronics 2025, 14, 1018. https://doi.org/10.3390/electronics14051018

AMA Style

Yan Z, Qiao H, Guo Z, Wang D, Feng Y. An Improved Second-Order Generalized Integrator Phase-Locked Loop with Frequency Error Compensation. Electronics. 2025; 14(5):1018. https://doi.org/10.3390/electronics14051018

Chicago/Turabian Style

Yan, Zhaoyang, Hanyi Qiao, Zongze Guo, Dongxu Wang, and Yidan Feng. 2025. "An Improved Second-Order Generalized Integrator Phase-Locked Loop with Frequency Error Compensation" Electronics 14, no. 5: 1018. https://doi.org/10.3390/electronics14051018

APA Style

Yan, Z., Qiao, H., Guo, Z., Wang, D., & Feng, Y. (2025). An Improved Second-Order Generalized Integrator Phase-Locked Loop with Frequency Error Compensation. Electronics, 14(5), 1018. https://doi.org/10.3390/electronics14051018

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