Chaos-Based Lightweight Cryptographic Algorithm Design and FPGA Implementation
<p>The lightweight ZUC algorithm structure diagram.</p> "> Figure 2
<p>The schematic diagram of data operation bit width.</p> "> Figure 3
<p>The extraction algorithm of chaotic sequences.</p> "> Figure 4
<p>Algorithm module top-level design diagram.</p> "> Figure 5
<p>Algorithm top-level architecture diagram.</p> "> Figure 6
<p>The RTL-level view of the algorithm.</p> "> Figure 7
<p>The state transfer diagram of ZFSM.</p> "> Figure 8
<p>Function Simulation Results.</p> "> Figure 9
<p>The top-level design of image encryption system.</p> "> Figure 10
<p>Image encryption system top-level architecture.</p> "> Figure 11
<p>The top-level RTL view of image encryption system.</p> "> Figure 12
<p>The ethernet transmission ILA capture.</p> "> Figure 13
<p>ILA capture based on initial vectors of high-dimensional chaotic sequence.</p> "> Figure 14
<p>Dynamic initial key generation for ILA capture based on plaintext images.</p> "> Figure 15
<p>LZUC-based keystream data generation for ILA crawling.</p> "> Figure 16
<p>LCD Display.</p> "> Figure 17
<p>Histograms of plaintext ciphertext images.</p> "> Figure 18
<p>Image encryption and decryption image correlation analysis.</p> ">
Abstract
:1. Introduction
- An effective lightweight ZUC cipher (LZUC) based on chaos is proposed. The stream cipher is based on the three-layer algorithm structure of the traditional ZUC cipher, optimizes the size of the state variables of the LFSR layer registers as appropriate, and proposes a chaos-based iterative scheme of the modulo operation for the problem such that the linearly driven part may not satisfy the modulo addition operation in the prime domain GF(231-1) after the size of the state variables is changed; for the problem of how to introduce a nonlinear function F-layer into the chaotic system, a chaotic sequence selection algorithm is proposed;
- The lightweight implementation of digital chaotic systems is accomplished through the knowledge of digital circuits. The improvement of the lightweight discrete chaotic system is combined to ensure the safety of the system while achieving the lightweight purpose more conveniently; a scheme that can ensure the accuracy of the chaotic system in the digital implementation is proposed to enhance the degradation resistance of the discrete chaotic system;
- The above scheme and the modular design of LZUC are completed and the corresponding simulation results are given. NIST statistical tests are performed on the key sequence output from this cipher and its security analyzed in terms of information entropy and resistance to weak key analysis, guessing–determination analysis, time–stored data trade-off analysis, and algebraic analysis of these typical attacks;
- An image encryption system based on LZUC cipher and four-dimensional hyperchaotic Lorenz system is designed and the hardware implementation of FPGA is completed. The embedded logic analyzer (ILA) of Vivado platform is used to capture the key data in the image encryption system in real time to verify the reliability of the system. The histogram analysis and correlation calculation are used to analyze the encryption effect and security of the image encryption system and further verify the feasibility of the LZUC cipher. Combined with the final LCD display, it can be accurately visualized that the lightweight cipher has good performance.
2. Lightweight ZUC Algorithm
2.1. Logistic Chaotic Map
2.1.1. Fixed-Point Decimal Arithmetic Method Based on Hardware
- Define the register variable r to represent a fixed-point decimal in mQa format, and round it to represent a fixed-point decimal in (m + 1)Qb format with the register variable r′. When the highest bit of the register variable r is 0:
- Define the register variable r′ to represent a fixed-point decimal in (m + 1)Qb format and use the register variable r″ to represent a fixed-point decimal in nQb format after saturation truncation. When the register variable r′[m:n−1] = (m − n + 1)′d0 or r′[m:n − 1] = (m − n + 1)′d(2(m − n + 1) − 1):
2.1.2. Lightweight Algorithm for Chaotic System
2.2. Lightweight Key Loading
2.3. Lightweight Construction of LFSR
2.4. Lightweight Nonlinear Function
Algorithm 1: Chaos-based transformation process of nonlinear function F |
1: |
2: |
3: |
4: |
5: |
6: |
7: |
8: |
2.5. Nonlinear Sequence Extraction Based on Chaos
2.6. Lightweight Bit Reorganization
Algorithm 2: Bit reorganization of LZUC |
1: |
2: |
3: |
4: |
5: |
6: |
7: |
3. Implementation of LZUC Algorithm
3.1. RTL Design and Verification
3.2. Hardware Implementation Analysis
4. Key Sequence Analysis of LZUC
4.1. NIST (National Institute of Standards and Technology) Statistical Tests
4.2. Information Entropy Analysis
4.3. Security Evaluation
4.3.1. Weak Key Analysis
4.3.2. Guess and Determine Attack
4.3.3. Time–Memory Data Trade-Off Attack
4.3.4. Algebraic Attack
5. Implementation of Image Encryption System
5.1. RTL Design
- At the end of reset, the RGMII_RX module completes the conversion of plaintext data from the RGMII protocol to the GMII protocol. The CMB_16BIT module spells the plaintext data of two adjacent bytes output from the RGMII module into RGB data of RGB565 mode;
- The rising edge of the cmb_flag signal triggers the DYN_KEY module to start, generating a dynamic initial key and outputting it to the ENCRYP_IP module;
- The cryptographic core uses this initial key k and the iv generated by the four-dimensional Lorenz chaos sequence generator to initialize the LZUC lightweight cipher and store the output keystream in KEY_RAM for use. Meanwhile, the ASFIFO _16BIT module completes the transfer of RGB data across the clock domain and stores the image data in DDR3 memory;
- When the IMG_ENCRYP_FSM module detects that the empty signal is valid, it marks that the image data is completely stored in DDR3 memory at this time. The IMG_ENCRYP_FSM module controls DDR3 to read out the image RGB data after MIG IP processing and then input to VGA module to display the explicit image through LCD;
- At this time, when the system master controller detects a rising edge of the cipher_disp signal (indicating that the user presses the image encryption button), it will control the IMG_ENCODE encryption module to complete the heterogeneous encryption of the plaintext image and the key stream. The cipher data will be stored in DDR3 memory in real time;
- When DDR3 finishes storing the whole cipher image data, the IMG_ENCRYP_FSM module then reads the cipher data into the VGA module and finishes displaying the cipher image through the LCD.
5.2. Test and Board Level Verification
5.3. Ciphertext Image Analysis
5.3.1. Histogram Analysis
5.3.2. Adjacent Pixels Correlation Analysis
6. Conclusions
Author Contributions
Funding
Institutional Review Board Statement
Informed Consent Statement
Data Availability Statement
Conflicts of Interest
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Objects | Slice LUTs | Slice Registers | DSP |
---|---|---|---|
Traditional scheme | 362 | 66 | 20 |
Lightweight scheme | 224 | 64 | 16 |
Cipher | Slice LUTs | Slice Registers | Slice |
---|---|---|---|
LAES [42] | 9175 | - | - |
Grain-128a [43] | 297 | 274 | - |
AES [44] | 9516 | - | - |
Mickey-128 [45] | 596 | 321 | 200 |
Trivium [46] | 182 | 289 | 41 |
Decim-128 | 683 | 330 | - |
ZUC | 960 | 631 | 324 |
LZUC (our work) | 668 | 437 | 277 |
Cipher | LFSR | BR | F | CHAOS |
---|---|---|---|---|
ZUC | 662 | 0 | 417 | - |
LZUC | 469 | 0 | 39 | 221 |
Lightweight proportion | 29.15% | 0 | 37.65% |
Cipher | Total Delay (ns) | Logic Delay (ns) | Net Delay (ns) |
---|---|---|---|
ZUC | 18.212 | 8.494 | 9.718 |
LZUC | 16.816 | 7.880 | 8.936 |
Test Project | p-Values | Pass Proportion |
---|---|---|
Approximate Entropy | 0.515932 | 100/100 |
Block Frequency | 0.857405 | 100/100 |
Cumulative Sum | 0.412490 | 100/100 |
FFT | 0.063180 | 100/100 |
Frequency | 0.552568 | 99/100 |
Linear Complexity | 0.380717 | 100/100 |
Longest Run | 0.203252 | 100/100 |
Non-Overlapping Template | 0.857405 | 99/100 |
Overlapping Template | 0.739918 | 100/100 |
Random Excursion (x = −1) Test | 0.696376 | 100/100 |
Random Excursions Variant (x = 1) Test | 0.858470 | 99/100 |
Rank | 0.627655 | 100/100 |
Runs | 0.809915 | 100/100 |
Serial | 0.462821 | 100/100 |
Universal | 0.223755 | 100/100 |
LZUC | Probability P | Information Quantity (Bit) | Information Entropy (Bit) |
---|---|---|---|
0 | 0.499926 | 1.00021 | 0.50003 |
1 | 0.500074 | 0.99979 | 0.49996 |
Cipher | Information Entropy |
---|---|
Logistic | 0.5951 |
Logic [35] | 0.9238 |
LZUC | 0.9999 |
Signals | I/O | Signal Definition |
---|---|---|
sys_clk_p/n | In | Differential clock |
rst_n | In | Reset, active low level |
plain_disp | In | Decryption control |
cipher_disp | In | Encrypted control |
rgmii_rxc | In | Ethernet receiver clock |
rgmii_rx_ctl | In | Valid flag bit for ethernet data |
rgmii_rd[3:0] | In | RGMII Input data |
vga_hs | Out | Line synchronization signal |
vga_vs | Out | Field synchronization signal |
vga_blk | Out | Field blanking signal |
tft_bl | Out | Backlight control |
tft_clk | Out | LCD clock |
vga_rgb[23:0] | Out | RGB data |
User_Interface | Out | User interface |
Test Object | Color Component | Horizontal Direction | Vertical Direction | Diagonal Direction |
---|---|---|---|---|
Plaintext image | R | 0.98567 | 0.97833 | 0.96864 |
G | 0.97411 | 0.96217 | 0.94749 | |
B | 0.96279 | 0.95008 | 0.93661 | |
Ciphertext image | R | 0.00531 | −0.00277 | 0.00120 |
G | −0.00869 | 0.00495 | −0.00039 | |
B | −0.00252 | 0.00325 | −0.00262 |
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Guang, Y.; Yu, L.; Dong, W.; Wang, Y.; Zeng, J.; Zhao, J.; Ding, Q. Chaos-Based Lightweight Cryptographic Algorithm Design and FPGA Implementation. Entropy 2022, 24, 1610. https://doi.org/10.3390/e24111610
Guang Y, Yu L, Dong W, Wang Y, Zeng J, Zhao J, Ding Q. Chaos-Based Lightweight Cryptographic Algorithm Design and FPGA Implementation. Entropy. 2022; 24(11):1610. https://doi.org/10.3390/e24111610
Chicago/Turabian StyleGuang, Yerui, Longfei Yu, Wenjie Dong, Ya Wang, Jian Zeng, Jiayu Zhao, and Qun Ding. 2022. "Chaos-Based Lightweight Cryptographic Algorithm Design and FPGA Implementation" Entropy 24, no. 11: 1610. https://doi.org/10.3390/e24111610