Optimization of Advanced Encryption Standard (AES) Using Vivado High Level Synthesis (HLS)

9 pages•Published: March 13, 2019

Luka Daoud, Fady Hussein and Nader Rafla

Abstract

Advanced Encryption Standard (AES) represents a fundamental building module of many network security protocols to ensure data confidentiality in various applications ranging from data servers to low-power hardware embedded systems. In order to optimize such hardware implementations, High-Level Synthesis (HLS) provides flexibility in designing and rapid optimization of dedicated hardware to meet the design constraints. In this paper, we present the implementation of AES encryption processor on FPGA using Xilinx Vivado HLS. The AES architecture was analyzed and designed by loop unrolling, and inner-round and outer-round pipelining techniques to achieve a maximum throughput of the AES algorithm up to 1290 Mbps (Mega bit per second) with very significant low resources of 3.24% slices of the FPGA, achieving 3 Mbps per slice area.

Keyphrases: advanced encryption standard, aes, fpga., high level synthesis, hls, optimization

In: Gordon Lee and Ying Jin (editors). Proceedings of 34th International Conference on Computers and Their Applications, vol 58, pages 36-44.

Links:	https://easychair.org/publications/paper/b2ZJ
	https://doi.org/10.29007/x3tx

BibTeX entry

@inproceedings{CATA2019:Optimization_Advanced_Encryption_Standard,
  author    = {Luka Daoud and Fady Hussein and Nader Rafla},
  title     = {Optimization of Advanced Encryption Standard (AES) Using Vivado High Level Synthesis (HLS)},
  booktitle = {Proceedings of 34th International Conference on Computers and Their Applications},
  editor    = {Gordon Lee and Ying Jin},
  series    = {EPiC Series in Computing},
  volume    = {58},
  publisher = {EasyChair},
  bibsource = {EasyChair, https://easychair.org},
  issn      = {2398-7340},
  url       = {/publications/paper/b2ZJ},
  doi       = {10.29007/x3tx},
  pages     = {36-44},
  year      = {2019}}

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