基于FPGA的7-Zip加密文档高能效口令恢复方法

计算机科学 ›› 2020, Vol. 47 ›› Issue (1): 321-328.doi: 10.11896/jsjkx.190100027

• 信息安全 • 上一篇

基于FPGA的7-Zip加密文档高能效口令恢复方法

陈晓杰¹,周清雷¹,李斌^1,2

(郑州大学信息工程学院郑州450001)¹;
(解放军信息工程大学数学工程与先进计算国家重点实验室郑州450001)²

收稿日期:2019-01-05 发布日期:2020-01-19
通讯作者: 周清雷(ieqlzhou@zzu.edu.cn)
基金资助:
国家重点研发计划项目(2016YFB0800100);国家自然科学基金面上项目(61572444)

Energy-efficient Password Recovery Method for 7-Zip Document Based on FPGA

CHEN Xiao-jie¹,ZHOU Qing-lei¹,LI Bin^1,2

(School of Information Engineering,Zhengzhou University,Zhengzhou 450001,China)¹;
(State Key Laboratory of Mathematical Engineering and Advanced Computing,Information Engineering University,Zhengzhou 450001,China)²

Received:2019-01-05 Published:2020-01-19
About author:CHEN Xiao-jie,born in 1993,postgra-duate,is not member of China ComputerFederation (CCF).His main research interests include information security;ZHOU Qing-lei,born in 1962,Ph.D,professor,Ph.D supervisor,is member of China Computer Federation (CCF).His main research interests include information security,automata theory and computational complexity theory.
Supported by:
This work was supported by the National Key R&D Program of China (2016YFB0800100) and General Program of National Natural Science Foundation of China (61572444).

摘要/Abstract

摘要： 随着7-Zip压缩软件的广范使用,破解7-Zip加密文档的口令对信息安全有着非常重要的意义。目前,破解7-Zip加密文档主要采用CPU和GPU平台,而潜在的口令空间大,计算复杂度高,在有限的时间内找到正确的口令需要更高性能的计算平台。因此,文中通过分析解密算法的PMC特性,采用可重构的FPGA硬件计算平台,使用流水线技术来实现数据拼接和SHA-256算法,并利用预计算和CSA方法优化SHA-256算法的关键路径,同时使用双端口RAM存储校验数据,从而满足算法的计算需求和存储需求,实现高效能的7-Zip解密算法。实验数据表明,文中提出的优化方法能大幅提升SHA-256算法的性能,使其吞吐量达到110.080Gbps,并且通过多种方法对解密算法进行优化,最终破解10位长度口令的速率达到了10608个/s,是CPU的226倍,GPU的1.4倍,且能效比是GPU的8倍,极大地提升了算法的性能,降低了高功耗需求。

关键词: 7-Zip解密, SHA-256, 高能效口令恢复, 可重构, 流水线, 双端口RAM

Abstract: With the wide range of 7-Zip compression software,7-Zip password cracking is very important for information security.Currently,cracking 7-Zip encryption documents mainly uses CPU and GPU platforms,and the potential for a large password space and high computational complexity requires a higher performance computing platform to find the correct password within a limited time.Therefore,by analyzing PMC characteristics of decryption algorithm,this paper adopted reconfigurable FPGA hardware computing platform,uses pipeline technology to realize data splicing and SHA-256 algorithm,used precomputation and CSA method to optimize the key path of SHA-256 algorithm,and used dual-port RAM to store verification data,thus satisfying the computational and storage requirements of the algorithm and realizing high-performance 7-Zip decryption algorithm.The experimental data show that the optimization method in this paper can greatly improve the performance of SHA-256 algorithm,making it throughput reach 110.080Gbps.The decryption algorithm is optimized by various methods,and finally the 10bit password is cracked to10608 per second,226 times that of the CPU,1.4 times that of the GPU,and 8 times that of the GPU, which greatly improves the performance and reduces the demand for high power consumption.

Key words: 7-Zip decryption, Dual port RAM, Energy-efficient password recovery, Pipeline, Reconfigurable, SHA-256

中图分类号:

TP309

陈晓杰,周清雷,李斌. 基于FPGA的7-Zip加密文档高能效口令恢复方法[J]. 计算机科学, 2020, 47(1): 321-328. https://doi.org/10.11896/jsjkx.190100027

CHEN Xiao-jie,ZHOU Qing-lei,LI Bin. Energy-efficient Password Recovery Method for 7-Zip Document Based on FPGA[J]. Computer Science, 2020, 47(1): 321-328. https://doi.org/10.11896/jsjkx.190100027

参考文献

[1]CHEN F T,YUAN J L.Enhanced Key Derivation Function of HMAC-SHA-256 Algorithm in LTE Network[C]∥Fourth International Conference on Multimedia Information NETWORKING and Security.IEEE Computer Society,Washingdon,DC,USA,2012:15-18.
[2]ZHAO X J,GUO S Z,WANG T,et al.Improved Cache trace driven attack on AES and CLEFIA[J].Journal on Communications,2011,32(8):101-110.
[3]WANG D,JIAN G P,HUANG X Y,et al.Zipf’s Law in Passwords[J].IEEE Transactions on Information Forensics and Security,2017,12(11):2776-2791.
[4]MA J,YANG W N,LUO M,et al.A Study of Probabilistic Password Models[C]∥IEEE Symposium on Security and Privacy.USA:IEEE,2014:689-704.
[5]WANG D,ZHANG Z J,WANG P,et al.Targeted Online Password Guessing:An Underestimated Threat[C]∥Proceedings of the 2016 ACM SIGSAC Conference on Computer and Communications Security.New York:USA,ACM,2016:1242-1254.
[6]WANG P,WANG D,HUANG X Y.Advances in password security[J].Journal of Computer Research and Development,2016,53(10):2173-2188.
[7]KOZIEL B,AZARDERAKHSH R,KERMANI M M,et al. Post-Quantum Cryptography on FPGA Based on Isogenies on Elliptic Curves[J].IEEE Transactions on Circuits and Systems I:Regular Papers,2017,64(1):86-99.
[8]ZHANG C,LI P,SUN G,et al.Optimizing FPGA-based Acce- lerator Design for Deep Convolutional Neural Networks[C]∥Proceesing of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays.New York:ACM,2015:161-170.
[9]DABHADE S D,RATHNA G N,CHAUDHURY K N.A Reconfigurable and Scalable FPGA Architecture for Bilateral Filtering[J].IEEE Transactions on Industrial Electronics,2018,65:1459-1469.
[10]LIU P,LI S,DING Q.An Energy-Efficient Accelerator Based on Hybrid CPU-FPGA Devices for Password Recovery[J].IEEE Transactions on Computers,2019,68(2):170-181.
[11]ZHOU B,ZHANG Y Q,AN X J,et al.Optimization of RAR password brute-force cracking based on OpenCL [C]∥High-Performance Computing China 2014.2014:871-874.
[12]AN X J,JIA H P,ZHANG Y Q.Optimized Password Recovery for Encrypted RAR on GPUs[C]∥IEEE InternationalConfe-rence on High PERFORMANCE Computing and Communications.IEEE Computer Society,2015:591-598.
[13]LIU Z L,DONG X,LI D F.On the Hardware Implementations of the SHA-2(256,384,512) Hash Function[J].Microelectro-nics & Computer,2012,29(12):51-54.
[14]ALGREDO-BADILLO I,FEREGRINO-URIBE C,CUMPLIDO R,et al.FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256[J].Microprocessors & Microsystems,2013,37(6／7):750-757.
[15]JULIATO M,GEBOTYS C.A Quantitative Analysis of a Novel SEU-Resistant SHA-2 and HMAC Architecture for Space Missions Security[J].IEEE Transactions on Aerospace &Electronic Systems,2013,49(3):1536-1554.
[16]MICHAIL H E,ATHANASIOU G S,KELEFOURAS V,et al.On the exploitation of a high-throughput SHA-256 FPGA design for HMAC[J].Acm Transactions on Reconfigurable Technology & Systems,2012,5(1):1-28.
[17]TAN J,ZHOU Q L,SI X M,et al.Implementation and improvement of full-pipeline MD5 algorithm based on mimic compiter[J].Journal of Chinese Computer Systems,2017,38(6):1216-1220.
[18]LEI Y W,DOU Y,GUO S.High precision Scientific Computation Accumulator on FPGA[J].Chinese Journal of Computers,2012,35(1):112-122.
[19]WU Q,WANG X W,HUANG M.OpenFlow Switch Packets Pipeline Processing Mechanism Based on SDN[J].Computer Science,2018,45(10):295-299.
[20]LI Y,ZHANG D X,YU F.Technology Mapping of FPGA On-Chip-RAM in RTL Synthesis[J].Acta Electronica Sinica,2016,44(11):2660-2667.
[21]YU X F,LIU X B,HU B L,et al.Design of FIFO in High Speed Data Storage System Based on FPGA[J].Nuclear Electronics & Detection Technology,2010,30(1):59-62.
[22]LI B,ZHOU Q L,SI X M.Mimic computing for password reco- very[J].Future Generation Computer Systems,2018,84:58-77.
[23]ZHANG K,GUO F,ZHENG W et al.Design of a Pipeline-Coupled Instruction Loop Cache for Many-Core Processors[J].Journal of Computer Research and Development,2017,54(4):813-820.
[24]LIN B,LI S S,LIAO X K,et al.Seadown:SLA-Aware Size-Sca- ling Power Management in Heterogeneous MapReduce Cluster[J].Chinese Journal of Camputers,2013,36(5):977-987.

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