Article

Free access

Improving the three instruction machine

Author:

FPCA '89: Proceedings of the fourth international conference on Functional programming languages and computer architecture

Pages 100 - 115

https://doi.org/10.1145/99370.99378

Published: 01 November 1989 Publication History

PDF eReader

References

[1]

P.J. Landin The mechanical evaluation of expressions Computer Journal, January, 1964.

Google Scholar

[2]

H.G. Baker List processing in Real Time on a Serial Computer Communications of the ACM, April, 1978.

Digital Library

Google Scholar

[3]

P. Hudak and D. Karanz A combinator-based compiler for a functional langtmge Proceedings of the Principles of Programming L~guages conference, January 1984.

Digital Library

Google Scholar

[4]

T. Johnsson Compiling Lazy Functional Languages PhD thesis, Chalmers University of Technology, 1987.

Google Scholar

[5]

L. Augustsson Compiling Lazy Functional Languages, Part II PhD thesis, Chalmers University of Technology, 1987.

Google Scholar

[6]

J. Fairbairn and S. C. Wray TIM: a simple abstract machine for executing supercombinators Proceedings of the Functional Programming and Computer Architecture conference, Portland, Oregon, September 1987.

Digital Library

Google Scholar

[7]

R.J.M. Hughes Compile-time analysis of functional programs Declarative Programming Workshop, Austin, Texas.

Google Scholar

[8]

G. Argo Refining the Three Instruction Machine unpublished draft

Google Scholar

[9]

A. Bloss and P. Hudak Path semantics Proceexlings of the Third Workshop on the Mathematical Foundations of Programming Language Semantics, 1988

Digital Library

Google Scholar

[10]

G. Burn, S.L. Peyton Jones and j. Robson The Spineless G-machine Proceedings of the Lisp and Functional Programming, Utah, 1988

Digital Library

Google Scholar

[11]

M.M. Ramaer A study of the Three Instruction Machine unpublished draft

Google Scholar

[12]

D. Wakeling and A. Dix Optimising partial applications in TIM unpublished draft

Google Scholar

Cited By

View all

Fourtounis GPapaspyrou NBerthold JSheeran MNewton R(2014)An efficient representation for lazy constructors using 64-bit pointersProceedings of the 3rd ACM SIGPLAN workshop on Functional high-performance computing10.1145/2636228.2636232(23-30)Online publication date: 3-Sep-2014
https://dl.acm.org/doi/10.1145/2636228.2636232
Crégut P(2007)Strongly reducing variants of the Krivine abstract machineHigher-Order and Symbolic Computation10.1007/s10990-007-9015-z20:3(209-230)Online publication date: 1-Sep-2007
https://dl.acm.org/doi/10.1007/s10990-007-9015-z
Friedman DGhuloum ASiek JWinebarger O(2007)Improving the lazy Krivine machineHigher-Order and Symbolic Computation10.1007/s10990-007-9014-020:3(271-293)Online publication date: 1-Sep-2007
https://dl.acm.org/doi/10.1007/s10990-007-9014-0
Show More Cited By

Index Terms

Improving the three instruction machine
1. Software and its engineering
  1. Software notations and tools
    1. Compilers
    2. General programming languages
      1. Language features
        Procedures, functions and subroutines
2. Theory of computation
  1. Semantics and reasoning
    1. Program constructs

Recommendations

Improving processor efficiency through enhanced instruction fetch
Automatic custom instruction identification for application-specific instruction set processors

The application-specific instruction set processors (ASIPs) have received more and more attention in recent years. ASIPs make trade-offs between flexibility and performance by extending the base instruction set of a general-purpose processor with custom ...
Increasing the instruction fetch rate via block-structured instruction set architectures
MICRO 29: Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture

To exploit larger amounts of instruction level parallelism, processors are being built with wider issue widths and larger numbers of functional units. Instruction fetch rate must also be increased in order to effectively exploit the performance ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

FPCA '89: Proceedings of the fourth international conference on Functional programming languages and computer architecture

November 1989

395 pages

ISBN:0897913280

DOI:10.1145/99370

Chairman:
Joseph E. Stoy

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 November 1989

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

FPCA89

Sponsor:

SIGPLAN
IFIP WG 2.8
SIGARCH

FPCA89: The International Conference on Functional Programming Languages & Computer Architectures

September 11 - 13, 1989

Imperial College, London, United Kingdom

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

11
Total Citations
View Citations
471
Total Downloads

Downloads (Last 12 months)73
Downloads (Last 6 weeks)13

Reflects downloads up to 17 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Fourtounis GPapaspyrou NBerthold JSheeran MNewton R(2014)An efficient representation for lazy constructors using 64-bit pointersProceedings of the 3rd ACM SIGPLAN workshop on Functional high-performance computing10.1145/2636228.2636232(23-30)Online publication date: 3-Sep-2014
https://dl.acm.org/doi/10.1145/2636228.2636232
Crégut P(2007)Strongly reducing variants of the Krivine abstract machineHigher-Order and Symbolic Computation10.1007/s10990-007-9015-z20:3(209-230)Online publication date: 1-Sep-2007
https://dl.acm.org/doi/10.1007/s10990-007-9015-z
Friedman DGhuloum ASiek JWinebarger O(2007)Improving the lazy Krivine machineHigher-Order and Symbolic Computation10.1007/s10990-007-9014-020:3(271-293)Online publication date: 1-Sep-2007
https://dl.acm.org/doi/10.1007/s10990-007-9014-0
Milikowski RVree W(2005)The G-line a distributed processor for graph reductionPARLE '91 Parallel Architectures and Languages Europe10.1007/BFb0035100(119-136)Online publication date: 23-Jun-2005
https://doi.org/10.1007/BFb0035100
Douence RFradet P(2005)Towards a taxonomy of functional language implementationsProgramming Languages: Implementations, Logics and Programs10.1007/BFb0026812(27-44)Online publication date: 16-Jun-2005
https://doi.org/10.1007/BFb0026812
Douence RFradet P(1998)A systematic study of functional language implementationsACM Transactions on Programming Languages and Systems10.1145/276393.27639720:2(344-387)Online publication date: 1-Mar-1998
https://dl.acm.org/doi/10.1145/276393.276397
Chitnis SSatpathy MOberoi S(1995)Rationalized three instruction machineACM SIGPLAN Notices10.1145/202530.20253930:3(94-102)Online publication date: 1-Mar-1995
https://dl.acm.org/doi/10.1145/202530.202539
Chitnis SSatpathy MOberoi SErnst M(1995)Rationalized three instruction machinePapers from the 1995 ACM SIGPLAN workshop on Intermediate representations10.1145/202529.202539(94-102)Online publication date: 1-Mar-1995
https://dl.acm.org/doi/10.1145/202529.202539
Oberoi SNagaraja G(1993)Compiling relative set abstractionsProceedings of TENCON '93. IEEE Region 10 International Conference on Computers, Communications and Automation10.1109/TENCON.1993.320020(435-438)Online publication date: 1993
https://doi.org/10.1109/TENCON.1993.320020
Milikowski RVree W(1991)The G-Line a Distributed Processor for Graph ReductionParle ’91 Parallel Architectures and Languages Europe10.1007/978-3-662-25209-3_9(119-136)Online publication date: 1991
https://doi.org/10.1007/978-3-662-25209-3_9
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Improving processor efficiency through enhanced instruction fetch

Automatic custom instruction identification for application-specific instruction set processors

Increasing the instruction fetch rate via block-structured instruction set architectures