Article

Closed-form expressions of distributed RLC interconnects for analysis of on-chip inductance effects

Authors:

Hideki AsaiAuthors Info & Claims

DAC '04: Proceedings of the 41st annual Design Automation Conference

Pages 810 - 813

https://doi.org/10.1145/996566.996783

Published: 07 June 2004 Publication History

Abstract

The closed-form expressions of distributed RLC interconnects are proposed for analysis of on-chip inductance effects in order to insert optimally the repeaters. The transfer function of a circuit with driver-interconnect-load structure is approximated by the 5th order rational functions. The step responses computed by using the proposed expressions give the good agreement with the SPICE simulations.

References

[1]

M. Kammon, M. J. Tsuk, and J. K. White, "FASTHENRY: A multipole-accelerated 3-D inductance extraction program," IEEE Trans. Microwave Theory Techn., vol. 42, no. 1, pp. 1750--1758, Sept. 1994.

[2]

E. E. Davidson and B. D. McCredie, and W. V. Vilkelis. "Long lossy lines (L3) and their impact upon large chip performance," IEEE Trans. Components, Packaging, and Manufacturing Technology, Part B. Advanced Packaging., vol. 20, pp. 361--375, Nov. 1998.

Digital Library

[3]

T. Sakurai, "Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSI's," IEEE Trans. Electron. Devices, vol. 40, no. 1, pp. 118--124, Jan. 1993.

[4]

K. Banerjee and A. Mehrotra, "Analysis of on-chip inductance effects for distributed RLC interconnects," IEEE Trans. Computer-Aided Design, vol. 21, no. 8, pp. 904--915, Aug. 2002.

Digital Library

[5]

Y. I. Ismail and E. G. Friedman, "Effects of inductance on the propagation delay and repeater insertion in VLSI circuits," IEEE Trans. Computer-Aided Design, vol. 8, no. 2, pp. 195--206, Apr. 2000.

Digital Library

[6]

L. T. Pillage and R. A. Rohrer, "Asymptotic waveform evaluation for timing analysis," IEEE Trans. Computer-Aided Design, vol. 9, no. 4, pp. 352--366, Apr. 1990.

Digital Library

[7]

E. Chiprout and M. S. Nakhla, "Analysis of interconnect networks using complex frequency hopping (CFH)," IEEE Trans. Computer-Aided Design, vol. 14, no. 2, pp. 186--220, Feb. 1995.

Digital Library

[8]

P. Feldmann and R. W. Freund, "Efficient linear analysis by Pade approximation via the Lanczos process," IEEE Trans. Computer-Aided Design, vol. 14, no. 5, pp. 639--649, May 1995.

Digital Library

[9]

L. M. Silveira, M. Kamon, I. Elfadel, and J. White, "A coordinate-transformed Arnoldi algorithm for generating guaranteed stable reduced-order models of RLC circuits," in Proc. ICCAD'96, pp. 288--294, 1996.

Digital Library

[10]

A. Odabasioglu, M. Celik, and L. T. Pilleggi, "PRIMA: passive reduced-order interconnect macromodeling algorithm," IEEE Trans. Computer-Aided Design, vol. 17, no. 8, pp. 645--654, Aug. 1998.

Digital Library

[11]

Y. I. Ismail and E. G. Friedman, "DTT: direct truncation of the transfer function-- alternative to moment matching for tree structured interconnect," IEEE Trans. Computer-Aided Design, vol. 21, no. 2, pp. 131--144, Feb. 2002.

Digital Library

[12]

D. H. Xie and M. Nakhla, "Delay and crosstalk simulation of high-speed VLSI interconnects with nonlinear terminations," IEEE Trans. Computer-Aided Design, vol. 12, no. 11, pp. 1798--1811, Nov. 1993.

Digital Library

[13]

Y. Tanji, A. Ushida, and M. S. Nakhla, "Passive closed-form expression of RLCG transmission lines," in Proc. ISCAS'02, vol. 3, pp. 795--798, May 2002.

[14]

S. Moriguchi, K. Udagawa, S. Ichimatsu, Suugaku Koushiki II, Kadokawa, Tokyo, 1957 (in Japanese).

[15]

J. Vlach and K. Singhal, Computer Methods for Circuits Analysis and Design, New York: Van Nostrand Reinholdt, 1983.

Digital Library

[16]

A. Dounavis, R. Achar, and M. Nakhla, "Efficient passive circuit models for distributed networks with frequency-dependent parameters," IEEE Trans. Microwave Theory Tech., vol. 23, pp. 382--392, Aug 2000.

[17]

Int. Technol. Roadmap for Semiconductors (ITRS), 1999.

Cited By

Keran MDounavis A(2023) An Analytic RLC Model for Coupled Interconnects Which Uses a Numerical Inverse Laplace Transform IEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.328873231:10(1497-1508)Online publication date: Oct-2023
https://doi.org/10.1109/TVLSI.2023.3288732
Malvika Kumar VMummaneni K(2023)Delay and Overshoot Modelling of Asymmetric T-Tree InterconnectsInterconnect Technologies for Integrated Circuits and Flexible Electronics10.1007/978-981-99-4476-7_2(9-19)Online publication date: 22-Sep-2023
https://doi.org/10.1007/978-981-99-4476-7_2
Choudhary SQureshi S(2015)Design, Modelling and Simulation of H-Tree Clock Distribution NetworksAustralian Journal of Electrical and Electronics Engineering10.1080/1448837X.2010.114642777:3(257-264)Online publication date: 22-Sep-2015
https://doi.org/10.1080/1448837X.2010.11464277
Show More Cited By

Index Terms

Closed-form expressions of distributed RLC interconnects for analysis of on-chip inductance effects
1. Hardware
  1. Integrated circuits

Recommendations

Analysis of on-chip inductance effects for distributed RLC interconnects

This paper introduces an accurate analysis of on-chip inductance effects for distributed RLC interconnects that takes the effect of both the series resistance and the output parasitic capacitance of the driver into account. Using rigorous first ...
Inductance Analysis of On-Chip Interconnects
EDTC '97: Proceedings of the 1997 European conference on Design and Test

It is generally believed that inductance analysis of on-chip interconnect becomes important when the clock frequency of circuits rises above GHz level. In this paper we show that this perception is not true. It becomes necessary to consider the ...
Analysis of on-chip inductance effects using a novel performance optimization methodology for distributed RLC interconnects
DAC '01: Proceedings of the 38th annual Design Automation Conference

This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new optimization technique has been employed to analyze the impact of line ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '04: Proceedings of the 41st annual Design Automation Conference

June 2004

1002 pages

ISBN:1581138288

DOI:10.1145/996566

General Chair:
Sharad Malik
Princeton University, Princeton, NJ
,
Program Chairs:
Limor Fix
Intel Semiconductors Ltd., Haifa, Israel
,
Andrew B. Kahng
University of California at San Diego, La Jolla, CA

Copyright © 2004 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 07 June 2004

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

DAC04

Sponsor:

DAC04: The 41st Annual Design Automation Conference 2004

June 7 - 11, 2004

CA, San Diego, USA

Acceptance Rates

Overall Acceptance Rate 1,264 of 4,035 submissions, 31%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

7
Total Citations
View Citations
335
Total Downloads

Downloads (Last 12 months)2
Downloads (Last 6 weeks)0

Reflects downloads up to 16 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Keran MDounavis A(2023) An Analytic RLC Model for Coupled Interconnects Which Uses a Numerical Inverse Laplace Transform IEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.328873231:10(1497-1508)Online publication date: Oct-2023
https://doi.org/10.1109/TVLSI.2023.3288732
Malvika Kumar VMummaneni K(2023)Delay and Overshoot Modelling of Asymmetric T-Tree InterconnectsInterconnect Technologies for Integrated Circuits and Flexible Electronics10.1007/978-981-99-4476-7_2(9-19)Online publication date: 22-Sep-2023
https://doi.org/10.1007/978-981-99-4476-7_2
Choudhary SQureshi S(2015)Design, Modelling and Simulation of H-Tree Clock Distribution NetworksAustralian Journal of Electrical and Electronics Engineering10.1080/1448837X.2010.114642777:3(257-264)Online publication date: 22-Sep-2015
https://doi.org/10.1080/1448837X.2010.11464277
Chen JSun JWang JNam GSaxena P(2009)Robust interconnect communication capacity algorithm by geometric programmingProceedings of the 2009 international symposium on Physical design10.1145/1514932.1514938(19-26)Online publication date: 29-Mar-2009
https://dl.acm.org/doi/10.1145/1514932.1514938
Roy SDounavis A(2009)Closed-form delay and crosstalk models for RLC on-chip interconnects using a matrix rational approximationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.202635428:10(1481-1492)Online publication date: 1-Oct-2009
https://dl.acm.org/doi/10.1109/TCAD.2009.2026354
Singhal RChoi GMahapatra RHassoun S(2006)Information theoretic approach to address delay and reliability in long on-chip interconnectsProceedings of the 2006 IEEE/ACM international conference on Computer-aided design10.1145/1233501.1233563(310-314)Online publication date: 5-Nov-2006
https://dl.acm.org/doi/10.1145/1233501.1233563
Wang BMazumder P(2005)EM Wave Coupling Noise Modeling Based on Chebyshev Approximation and Exact Moment FormulationProceedings of the conference on Design, Automation and Test in Europe - Volume 210.1109/DATE.2005.131(976-981)Online publication date: 7-Mar-2005
https://dl.acm.org/doi/10.1109/DATE.2005.131

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents