Article

RESTA: a robust and extendable symbolic timing analysis tool

Authors:

Joel GrodsteinAuthors Info & Claims

GLSVLSI '04: Proceedings of the 14th ACM Great Lakes symposium on VLSI

Pages 407 - 412

https://doi.org/10.1145/988952.989050

Published: 26 April 2004 Publication History

Abstract

Successful timing analysis for high-speed integrated circuits requires accurate delay computation. However, full-custom circuits popular in today's CPU designs make this difficult. A good circuit-level static timing analysis tool should 1) consider both internally or externally specified input constraints; 2) handle a wide range of circuit structures; and 3) have a robust underlying framework that can be applied independent of the actual device model. In this paper, we present RESTA, a Robust and Extendable Symbolic Timing Analysis tool that aims to address these three goals. RESTA estimates the delay for all valid input assignments, while naturally handling input constraints. We start with a simple linear resistor model for transistors and from there apply various heuristics to improve the delay estimation for the circuits without altering the symbolic algorithms. Our worst-case delay estimates are within 10% of SPICE for over 90% of the circuits we simulated.

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Cited By

Tadesse DBahar RGrodstein J(2011)Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision ProblemsJournal of Electronic Testing: Theory and Applications10.1007/s10836-011-5205-z27:2(123-136)Online publication date: 1-Apr-2011
https://dl.acm.org/doi/10.1007/s10836-011-5205-z
Tadesse DSheffield DLenge EBahar RGrodstein JLauwereins RMadsen J(2007)Accurate timing analysis using SAT and pattern-dependent delay modelsProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266586(1018-1023)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266586
Tadesse DSheffield DLenge EBahar RGrodstein J(2007)Accurate Timing Analysis using SAT and Pattern-Dependent Delay Models2007 Design, Automation & Test in Europe Conference & Exhibition10.1109/DATE.2007.364427(1-6)Online publication date: Apr-2007
https://doi.org/10.1109/DATE.2007.364427
Show More Cited By

Index Terms

RESTA: a robust and extendable symbolic timing analysis tool
1. Hardware
  1. Hardware validation

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Information

Published In

cover image ACM Conferences

GLSVLSI '04: Proceedings of the 14th ACM Great Lakes symposium on VLSI

April 2004

479 pages

ISBN:1581138539

DOI:10.1145/988952

General Chair:
David Garrett
Bell Labs Research, Lucent Technologies
,
Program Chairs:
John Lach
University of Virginia
,
Charles Zukowski
Columbia University

Copyright © 2004 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

Publication History

Published: 26 April 2004

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GLSVLSI04: Great Lakes Symposium on VLSI 2004

April 26 - 28, 2004

MA, Boston, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Tadesse DBahar RGrodstein J(2011)Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision ProblemsJournal of Electronic Testing: Theory and Applications10.1007/s10836-011-5205-z27:2(123-136)Online publication date: 1-Apr-2011
https://dl.acm.org/doi/10.1007/s10836-011-5205-z
Tadesse DSheffield DLenge EBahar RGrodstein JLauwereins RMadsen J(2007)Accurate timing analysis using SAT and pattern-dependent delay modelsProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266586(1018-1023)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266586
Tadesse DSheffield DLenge EBahar RGrodstein J(2007)Accurate Timing Analysis using SAT and Pattern-Dependent Delay Models2007 Design, Automation & Test in Europe Conference & Exhibition10.1109/DATE.2007.364427(1-6)Online publication date: Apr-2007
https://doi.org/10.1109/DATE.2007.364427
Miskov-Zivanov NMarculescu D(2006)Circuit Reliability Analysis Using Symbolic TechniquesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2006.88259225:12(2638-2649)Online publication date: Dec-2006
https://doi.org/10.1109/TCAD.2006.882592

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