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Performance evaluation of a commercial cache-coherent shared memory multiprocessor

Authors:

Rajeev Jog,

Philip L. Vitale,

James R. CallisterAuthors Info & Claims

ACM SIGMETRICS Performance Evaluation Review, Volume 18, Issue 1

Pages 173 - 182

https://doi.org/10.1145/98460.98756

Published: 01 April 1990 Publication History

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Abstract

This paper describes an approximate Mean Value Analysis (MVA) model developed to project the performance of a small-scale shared-memory commercial symmetric multiprocessor system. The system, based on Hewlett Packard Precision Architecture processors, supports multiple active user processes and multiple execution threads within the operating system.

Using detailed timing for hardware delays, a customized approximate closed queueing model is developed for the multiprocessor system. The model evaluates delays due to bus and memory contention, and cache interference. It predicts bus bandwidth requirements and utilizations for the bus and memory controllers. An extension to handle I/O traffic is outlined.

Applications are profiled on the basis of execution traces on uniprocessor systems to provide inputs parameters for the model. Performance effects of various detailed architectural tradeoffs (memory interleaving, lower memory latencies) are examined. The sensitivity of overall system performance to various parameters is explored. Preliminary measurements of uniprocessor systems are compared against the model predictions. A prototype multiprocessor system is under development. We intend to validate the modeling results against measurements.

References

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Cited By

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Albonesi DKoren I(1999)STATSJournal of Systems Architecture: the EUROMICRO Journal10.1016/S1383-7621(98)00052-645:12-13(1097-1110)Online publication date: 1-Jun-1999
https://dl.acm.org/doi/10.1016/S1383-7621%2898%2900052-6
Albonesi DKoren I(1996)A Mean Value Analysis Multiprocessor Model Incorporating Superscalar Processors and Latency Tolerating TechniquesInternational Journal of Parallel Programming10.1007/BF0335675024:3(235-263)Online publication date: 1-Jun-1996
https://dl.acm.org/doi/10.1007/BF03356750
Kulmala ASalminen ELehtoranta OHamalainen THannikainen M(2006)Impact of Shared Instruction Memory on Performance of FPGA-based MP-SoC Video EncoderProceedings of the 2006 IEEE Design and Diagnostics of Electronic Circuits and systems10.1109/DDECS.2006.1649571(57-62)Online publication date: 18-Apr-2006
https://dl.acm.org/doi/10.1109/DDECS.2006.1649571
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Index Terms

Performance evaluation of a commercial cache-coherent shared memory multiprocessor
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Interconnection architectures
2. Hardware
  1. Hardware test
    1. Test-pattern generation and fault simulation
  2. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

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Multiprocessor cache memory performance: characterization and optimization
Cache memory design and performance issues in shared-memory multiprocessors
Comparative performance evaluation of cache-coherent NUMA and COMA architectures
ISCA '92: Proceedings of the 19th annual international symposium on Computer architecture

Two interesting variations of large-scale shared-memory machines that have recently emerged are cache-coherent non-uniform-memory-access machines (CC-NUMA) and cache-only memory architectures (COMA). They both have distributed main memory and use ...

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cover image ACM SIGMETRICS Performance Evaluation Review

ACM SIGMETRICS Performance Evaluation Review Volume 18, Issue 1

May 1990

269 pages

ISSN:0163-5999

DOI:10.1145/98460

Editor:
M. K. Vernon

Issue’s Table of Contents

SIGMETRICS '90: Proceedings of the 1990 ACM SIGMETRICS conference on Measurement and modeling of computer systems
April 1990
273 pages
ISBN:0897913590
DOI:10.1145/98457
Chairman:
Gary J. Nutt
Univ. of Colorado, Boulder, CO

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 01 April 1990

Published in SIGMETRICS Volume 18, Issue 1

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Albonesi DKoren I(1999)STATSJournal of Systems Architecture: the EUROMICRO Journal10.1016/S1383-7621(98)00052-645:12-13(1097-1110)Online publication date: 1-Jun-1999
https://dl.acm.org/doi/10.1016/S1383-7621%2898%2900052-6
Albonesi DKoren I(1996)A Mean Value Analysis Multiprocessor Model Incorporating Superscalar Processors and Latency Tolerating TechniquesInternational Journal of Parallel Programming10.1007/BF0335675024:3(235-263)Online publication date: 1-Jun-1996
https://dl.acm.org/doi/10.1007/BF03356750
Kulmala ASalminen ELehtoranta OHamalainen THannikainen M(2006)Impact of Shared Instruction Memory on Performance of FPGA-based MP-SoC Video EncoderProceedings of the 2006 IEEE Design and Diagnostics of Electronic Circuits and systems10.1109/DDECS.2006.1649571(57-62)Online publication date: 18-Apr-2006
https://dl.acm.org/doi/10.1109/DDECS.2006.1649571
Albonesi DKoren I(1999)STATSJournal of Systems Architecture: the EUROMICRO Journal10.1016/S1383-7621(98)00052-645:12-13(1097-1110)Online publication date: 1-Jun-1999
https://dl.acm.org/doi/10.1016/S1383-7621%2898%2900052-6
Albonesi DKoren I(1996)A Mean Value Analysis Multiprocessor Model Incorporating Superscalar Processors and Latency Tolerating TechniquesInternational Journal of Parallel Programming10.1007/BF0335675024:3(235-263)Online publication date: 1-Jun-1996
https://dl.acm.org/doi/10.1007/BF03356750
Albonesi DKoren IBic LEvripidou PBöhm WGaudiot J(1995)An analytical model of high performance superscalar-based multiprocessorsProceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques10.5555/224659.224725(194-203)Online publication date: 27-Jun-1995
https://dl.acm.org/doi/10.5555/224659.224725
Huck JHays J(1993)Architectural support for translation table management in large address space machinesACM SIGARCH Computer Architecture News10.1145/173682.16512821:2(39-50)Online publication date: 1-May-1993
https://dl.acm.org/doi/10.1145/173682.165128
Huck JHays JSmith A(1993)Architectural support for translation table management in large address space machinesProceedings of the 20th annual international symposium on computer architecture10.1145/165123.165128(39-50)Online publication date: 1-Jun-1993
https://dl.acm.org/doi/10.1145/165123.165128
Muck JHays J(1993)Architectural Support For Translation Table Management In Large Address Space MachinesProceedings of the 20th Annual International Symposium on Computer Architecture10.1109/ISCA.1993.698544(39-50)Online publication date: 1993
https://doi.org/10.1109/ISCA.1993.698544

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Abstract

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Recommendations

Multiprocessor cache memory performance: characterization and optimization

Cache memory design and performance issues in shared-memory multiprocessors

Comparative performance evaluation of cache-coherent NUMA and COMA architectures

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