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Cache memories: A tutorial and survey of current research directions

Authors:

Robert P. Cook,

Cathy J. Linn,

Joseph L. Linn,

Terry M. WalkerAuthors Info & Claims

ACM '82: Proceedings of the ACM '82 conference

Pages 99 - 110

https://doi.org/10.1145/800174.809769

Published: 01 January 1982 Publication History

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Abstract

The tutorial presents a unified nomenclature for the description of cache memory systems. Using this foundation, examples of existing cache memory systems are detailed and compared.

The second presentation discusses a programmable cache memory architecture. In this architecture, intelligence is added to the cache to direct the activity between the cache and the main memory. Also to be described are heuristics for programming the cache which allow the additional power to be exploited.

The third presentation deals with innovations involving systems where the cache memory is not used as a simple high speed buffer for main memory. A straight forward example of this appears in IBM's Translation Lookaside Buffer on 370s with dynamic address translation hardware. Other examples are to be described include a cache system for the activation stack of a block structured language, a cache system to store subexpressions for an expression oriented architecture, and a multiprocessor architecture that relies on two levels of cache.

References

[1]

D. Ditzel and R. McLellan "Register Allocation for Free: The C Machine Stack Cache", ACM Symposium on Architectural Support for Programming Languages and Operating Systems, March, 1982.

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[2]

S. Harbison "A Computer Architecture for the Dynamic Optimization of High-Level Language Programs", Ph.D. Thesis, Carnegie-Mellon University Computer Science Department, Sept. 1980.

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[3]

S. Harbison "An Architectural Alternative to Optimizing Compilers", ACM Symposium on Architectural Support for Programming Languages and Operating Systems, March, 1982.

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[4]

J. Linn "The Carrick-on-Shannon Project Multiprocessor Model - Using Cache Memories to Reduce Memory Traffic" Tech. Report. 82-3-2, University of Southwestern Louisiana Computer Science Department, 1982.

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Cited By

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Lysko A(2012)Something different — Caching applied to calculation of impedance matrix elements2012 International Conference on Electromagnetics in Advanced Applications10.1109/ICEAA.2012.6328703(630-633)Online publication date: Sep-2012
https://doi.org/10.1109/ICEAA.2012.6328703
Asaduzzaman ASibai FRani M(2009)Impact of level-2 cache sharing on the performance and power requirements of homogeneous multicore embedded systemsMicroprocessors & Microsystems10.1016/j.micpro.2009.06.00133:5-6(388-397)Online publication date: 1-Aug-2009
https://dl.acm.org/doi/10.1016/j.micpro.2009.06.001

Index Terms

Cache memories: A tutorial and survey of current research directions
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

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While set-associative caches incur fewer misses than direct-mapped caches, they typically have slower hit times and higher power consumption, when multiple tag and data banks are probed in parallel. This paper presents the location cache structure which ...

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ACM '82: Proceedings of the ACM '82 conference

January 1982

235 pages

ISBN:0897910850

DOI:10.1145/800174

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 01 January 1982

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Lysko A(2012)Something different — Caching applied to calculation of impedance matrix elements2012 International Conference on Electromagnetics in Advanced Applications10.1109/ICEAA.2012.6328703(630-633)Online publication date: Sep-2012
https://doi.org/10.1109/ICEAA.2012.6328703
Asaduzzaman ASibai FRani M(2009)Impact of level-2 cache sharing on the performance and power requirements of homogeneous multicore embedded systemsMicroprocessors & Microsystems10.1016/j.micpro.2009.06.00133:5-6(388-397)Online publication date: 1-Aug-2009
https://dl.acm.org/doi/10.1016/j.micpro.2009.06.001

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References

Cited By

Index Terms

Recommendations

Multiprocessor cache memories: simulation and design

Analysis of multi-megabyte secondary CPU cache memories

Location cache: a low-power L2 cache system

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