Article

Distributed sleep transistor network for power reduction

Authors:

Changbo Long,

Lei HeAuthors Info & Claims

DAC '03: Proceedings of the 40th annual Design Automation Conference

Pages 181 - 186

https://doi.org/10.1145/775832.775879

Published: 02 June 2003 Publication History

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Abstract

Sleep transistors are effective to reduce dynamic and leakage power. The cluster-based design was proposed to reduce the sleep transistor area by clustering gates to minimize the simultaneous switching current per cluster and then inserting a sleep transistor per cluster. In the paper, we propose a novel distributed sleep transistor network (DSTN), and show that DSTN is intrinsically better than the cluster-based design in terms of the sleep transistor area and circuit performance. We reveal properties of optimal DSTN designs, and then develop an efficient algorithm for gate level DSTN synthesis. The algorithm obtains DSTN designs with up to 70.7% sleep transistor area reduction compared to cluster-based designs. Furthermore, we present custom layout designs to verify the area reduction by DSTN.

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Cited By

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Sharroush SAbdalla Y(2021)Optimum sizing of the sleep transistor in MTCMOS technologyAEU - International Journal of Electronics and Communications10.1016/j.aeue.2021.153882138(153882)Online publication date: Aug-2021
https://doi.org/10.1016/j.aeue.2021.153882
Peterson DBringmann O(2019)Power-Gating Models for Rapid Design Exploration2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)10.1109/NEWCAS44328.2019.8961232(1-4)Online publication date: Jun-2019
https://doi.org/10.1109/NEWCAS44328.2019.8961232
Taram MVenkat ATullsen D(2018)Mobilizing the micro-opsProceedings of the 45th Annual International Symposium on Computer Architecture10.1109/ISCA.2018.00058(624-637)Online publication date: 2-Jun-2018
https://dl.acm.org/doi/10.1109/ISCA.2018.00058
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Index Terms

Distributed sleep transistor network for power reduction
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design

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Information & Contributors

Information

Published In

DAC '03: Proceedings of the 40th annual Design Automation Conference

June 2003

1014 pages

ISBN:1581136889

DOI:10.1145/775832

General Chair:
Ian Getreu
Ambric Inc., Portland, OR
,
Program Chairs:
Limor Fix
Intel Semiconductors Ltd., Haifa, Israel
,
Luciano Lavagno
Cadence Berkeley Labs., Berkeley, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 02 June 2003

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SIGDA

DAC03: 2003 40th Annual Design Automation Conference

June 2 - 6, 2003

CA, Anaheim, USA

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DAC '03 Paper Acceptance Rate 152 of 628 submissions, 24%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Sharroush SAbdalla Y(2021)Optimum sizing of the sleep transistor in MTCMOS technologyAEU - International Journal of Electronics and Communications10.1016/j.aeue.2021.153882138(153882)Online publication date: Aug-2021
https://doi.org/10.1016/j.aeue.2021.153882
Peterson DBringmann O(2019)Power-Gating Models for Rapid Design Exploration2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)10.1109/NEWCAS44328.2019.8961232(1-4)Online publication date: Jun-2019
https://doi.org/10.1109/NEWCAS44328.2019.8961232
Taram MVenkat ATullsen D(2018)Mobilizing the micro-opsProceedings of the 45th Annual International Symposium on Computer Architecture10.1109/ISCA.2018.00058(624-637)Online publication date: 2-Jun-2018
https://dl.acm.org/doi/10.1109/ISCA.2018.00058
Cherupalli HDuwe HYe WKumar RSartori J(2017)Bespoke Processors for Applications with Ultra-low Area and Power ConstraintsACM SIGARCH Computer Architecture News10.1145/3140659.308024745:2(41-54)Online publication date: 24-Jun-2017
https://dl.acm.org/doi/10.1145/3140659.3080247
Cherupalli HDuwe HYe WKumar RSartori J(2017)Bespoke Processors for Applications with Ultra-low Area and Power ConstraintsProceedings of the 44th Annual International Symposium on Computer Architecture10.1145/3079856.3080247(41-54)Online publication date: 24-Jun-2017
https://dl.acm.org/doi/10.1145/3079856.3080247
Cherupalli HDuwe HYe WKumar RSartori J(2017)Enabling Effective Module-Oblivious Power Gating for Embedded Processors2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2017.48(157-168)Online publication date: Feb-2017
https://doi.org/10.1109/HPCA.2017.48
Bathla SPurohit N(2016)A high speed and low power 4-bit multiplier using FinFET technology2016 2nd International Conference on Next Generation Computing Technologies (NGCT)10.1109/NGCT.2016.7877390(61-64)Online publication date: Oct-2016
https://doi.org/10.1109/NGCT.2016.7877390
Tenentes VKhursheed SRossi DYang SAl-Hashimi B(2015)DFT Architecture With Power-Distribution-Network Consideration for Delay-Based Power Gating TestIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.244693934:12(2013-2024)Online publication date: Dec-2015
https://doi.org/10.1109/TCAD.2015.2446939
Uniyal SPandey SBhargave GKaur J(2015)4×4 Bit Multiplier using Adiabatic 2XOR and sleep mode transistor logic2015 International Conference on Signal Processing, Computing and Control (ISPCC)10.1109/ISPCC.2015.7375037(262-265)Online publication date: Sep-2015
https://doi.org/10.1109/ISPCC.2015.7375037
Tenentes VRossi DKhursheed SAl-Hashimi B(2015)Diagnosis of power switches with power-distribution-network consideration2015 20th IEEE European Test Symposium (ETS)10.1109/ETS.2015.7138774(1-6)Online publication date: May-2015
https://doi.org/10.1109/ETS.2015.7138774
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