Cited By
View all- Manxia Xiao Ning Li Fan Ye Junyan Ren (2007)A 1.2V low-jitter PLL for UWB2007 7th International Conference on ASIC10.1109/ICASIC.2007.4415632(323-326)Online publication date: Oct-2007
A dual band CMOS VCO with a balanced duty cycle buffer
Pages 277 - 280
Abstract
This paper proposes a dual band VCO with a standard 0.35? CMOS process to generate 1.07GHz and 2.06GHz. The proposed VCO architecture with 50% duty cycle circuit and a half adder(HA) is able to produce a frequency two times higher than that of the conventional VCOs. The measurement results demonstrate that the gain of VCO and power dissipation are 561MHz/V and 14.6mW, respectively. The phase noises of the dual band VCO are measured to be -99.05dBc/Hz and -94.9dBc/Hz at 2MHz offset from 1.07GHz and 2.06GHz.
References
[1]
B.Razavi, "Design of monolithic phase-locked loops and clock recovery circuits - a tutorial", in Monolithic Phase Locked Loops and Clock Recovery Circuits: Theory and Design, B.Razavi, Ed. New York, NY : IEEE Press, 1996.
[2]
Y.K.Moon, K.S.Yoon, "A 3.3V CMOS PLL with a self-Feedback VCO",IEICE Transaction on Fundamentals, vol.E83-A, No.12, pp2623--pp2626, Dec.2000.
[3]
H.Y.Yu, S.H.O, Y.C.Han, K.S.Yoon, "Design of 1.5V-3GHz CMOS Multi-changed Two Stage VCO", Proc. ITC-CSCC2000, July.2000.
[4]
Ali Hajimiri and Thomas H. Lee, The Design of Low Noise Oscillators, Kluwer Academic Publishers, 1999.
[5]
C. Park and B. Kim, "A Low-Noise, 900MHz VCO in 0.6mm CMOS", IEEE J.Solid-State Circuits, vol 34, pp. 586--590, May 1999.
Index Terms
- A dual band CMOS VCO with a balanced duty cycle buffer
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Published In
April 2003
320 pages
ISBN:1581136773
DOI:10.1145/764808
- General Chair:
- Mircea Stan,
- Program Chairs:
- David Garrett,
- Kazuo Nakajima
Copyright © 2003 ACM.
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Published: 28 April 2003
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View all- Manxia Xiao Ning Li Fan Ye Junyan Ren (2007)A 1.2V low-jitter PLL for UWB2007 7th International Conference on ASIC10.1109/ICASIC.2007.4415632(323-326)Online publication date: Oct-2007
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