Article

Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs

Authors:

Noureddine Chabini,

Ismaïl Chabini,

El Mostapha Aboulhamid,

Yvon SavariaAuthors Info & Claims

GLSVLSI '03: Proceedings of the 13th ACM Great Lakes symposium on VLSI

Pages 221 - 224

https://doi.org/10.1145/764808.764865

Published: 28 April 2003 Publication History

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Abstract

We address the problem of minimizing dynamic power consumption for single-phase synchronous digital designs, under timing constraints, using an unification of basic retiming and supply voltage scaling. We assume that the number of supply voltages and their values are known for each computation element. Our main objective is then to change the location of registers using basic retiming while maximizing the number of computation elements off critical paths that can operate under a low available supply voltage, and can lead to a maximum dynamic power saving. We address the problem at the system-level. We formulate the problem as a Mixed Integer Linear Program (MILP). The exact optimal solution for the problem is then guaranteed. We also devise an algorithm to compute bounds on the values assigned by basic retiming to each computational element. Besides helping to find the optimal solution to the problem, these bounds also allow to reduce the run-time for finding this solution. The proposed approach can produce converter-free designs and can also minimize short-circuit power consumption. Experimental results have shown that dynamic power consumption can be reduced by factors that range from 2.78% to 37.24% for single-phase designs with minimal clock period. For these experimental results, the run-time for solving the MILP is under 2min.

References

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Cited By

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Liu SMa YHong XWang YLin Y(2010)Simultaneous slack budgeting and retiming for synchronous circuits optimizationProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899733(49-54)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899733
Shenghua Liu Ma YHong XYu Wang (2010)Simultaneous slack budgeting and retiming for synchronous circuits optimization2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2010.5419919(49-54)Online publication date: Jan-2010
https://doi.org/10.1109/ASPDAC.2010.5419919
Chabini N(2009)Level-converter aware supply voltage scaling for reducing dynamic power dissipation in clocked sequential designs2009 International Conference on Multimedia Computing and Systems10.1109/MMCS.2009.5256722(102-105)Online publication date: Apr-2009
https://doi.org/10.1109/MMCS.2009.5256722
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Index Terms

Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs
1. Hardware

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Information & Contributors

Information

Published In

GLSVLSI '03: Proceedings of the 13th ACM Great Lakes symposium on VLSI

April 2003

320 pages

ISBN:1581136773

DOI:10.1145/764808

General Chair:
Mircea Stan
University of Virginia
,
Program Chairs:
David Garrett
Bell Labs Research, Lucent Technologies
,
Kazuo Nakajima
University of Maryland

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 28 April 2003

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GLSVLSI03

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GLSVLSI03: Great Lakes Symposium on VLSI 2003

April 28 - 29, 2003

D. C., Washington, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

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Liu SMa YHong XWang YLin Y(2010)Simultaneous slack budgeting and retiming for synchronous circuits optimizationProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899733(49-54)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899733
Shenghua Liu Ma YHong XYu Wang (2010)Simultaneous slack budgeting and retiming for synchronous circuits optimization2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2010.5419919(49-54)Online publication date: Jan-2010
https://doi.org/10.1109/ASPDAC.2010.5419919
Chabini N(2009)Level-converter aware supply voltage scaling for reducing dynamic power dissipation in clocked sequential designs2009 International Conference on Multimedia Computing and Systems10.1109/MMCS.2009.5256722(102-105)Online publication date: Apr-2009
https://doi.org/10.1109/MMCS.2009.5256722
Hu YLin YHe LTuan T(2008)Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retimingACM Transactions on Design Automation of Electronic Systems (TODAES)10.1145/1344418.134442613:2(1-29)Online publication date: 23-Apr-2008
https://dl.acm.org/doi/10.1145/1344418.1344426
Chabini N(2007)A Heuristic for reducing dynamic power dissipation in clocked sequential designsProceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation10.5555/2391795.2391804(64-74)Online publication date: 3-Sep-2007
https://dl.acm.org/doi/10.5555/2391795.2391804
Chabini N(2007)A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential DesignsIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation10.1007/978-3-540-74442-9_7(64-74)Online publication date: 2007
https://doi.org/10.1007/978-3-540-74442-9_7
Ekpanyapong MLim SScheffer L(2006)Integrated retiming and simultaneous Vdd/Vth scaling for total power minimizationProceedings of the 2006 international symposium on Physical design10.1145/1123008.1123036(142-148)Online publication date: 9-Apr-2006
https://dl.acm.org/doi/10.1145/1123008.1123036
Allam ARamanujam J(2006)Simultaneous Peak and Average Power Optimization in Synchronous Sequential Designs Using Retiming and Multiple Supply Voltages2006 IEEE International Conference on IC Design and Technology10.1109/ICICDT.2006.220821(1-6)Online publication date: 2006
https://doi.org/10.1109/ICICDT.2006.220821
Fischer RBuchenrieder KNageldinger U(2005)Reducing the Power Consumption of FPGAs through RetimingProceedings of the 12th IEEE International Conference and Workshops on Engineering of Computer-Based Systems10.1109/ECBS.2005.58(89-94)Online publication date: 4-Apr-2005
https://dl.acm.org/doi/10.1109/ECBS.2005.58
Chabini NWolf WImai M(2004)An approach for reducing dynamic power consumption in synchronous sequential digital designsProceedings of the 2004 Asia and South Pacific Design Automation Conference10.5555/1015090.1015137(198-204)Online publication date: 27-Jan-2004
https://dl.acm.org/doi/10.5555/1015090.1015137
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Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling

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