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Timing verification by formal signal interaction modeling in a multi-level timing simulator

Authors:

A. J. StrojwasAuthors Info & Claims

DAC '89: Proceedings of the 26th ACM/IEEE Design Automation Conference

Pages 668 - 673

https://doi.org/10.1145/74382.74500

Published: 01 June 1989 Publication History

Abstract

A new multi-level macromodeling technique for timing simulation has been developed. This technique is based upon the modeling of the behavior of subcircuits under single input changes. The possible interactions between multiple input changes determine the range of validity of the models. A formal method for developing the model validity conditions is presented. This work establishes a bridge between timing analysis by using single input change models, and timing simulation which correctly models signal interactions. The availability of a formal criterion for the validity of the models allows the dynamic identification of the parts of the circuit that require more accurate models. As a result, the cost advantage of high level models can be fully exploited while still allowing critical interactions to be simulated with high accuracy.

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Cited By

Mendler Mvon Hanxleden RTraulsen CBenini LDe Micheli GAl-Hashimi BMueller W(2009)WCRT algebra and interfaces for Esterel-style synchronous processingProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874644(93-98)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874644
Mendler Mvon Hanxleden RTraulsen C(2009)WCRT algebra and interfaces for esterel-style synchronous processing2009 Design, Automation & Test in Europe Conference & Exhibition10.1109/DATE.2009.5090639(93-98)Online publication date: Apr-2009
https://doi.org/10.1109/DATE.2009.5090639
Liu LChen HDu D(2006)The calculation of signal stable ranges in combinational circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.29803713:8(1016-1023)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.298037
Show More Cited By

Index Terms

Timing verification by formal signal interaction modeling in a multi-level timing simulator
1. Hardware
  1. Hardware validation
    1. Functional verification
      1. Simulation and emulation
  2. Very large scale integration design

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Published In

cover image ACM Conferences

DAC '89: Proceedings of the 26th ACM/IEEE Design Automation Conference

June 1989

839 pages

ISBN:0897913108

DOI:10.1145/74382

Chairman:
Donald E. Thomas
Carnegie Mellon Univ., Pittsburgh, PA

Copyright © 1989 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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IEEE-CS\TCDA: TC Design Automation
SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 1989

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DAC89: The 26th ACM/IEEE-CS Design Automation Conference

June 25 - 28, 1989

Nevada, Las Vegas, USA

Acceptance Rates

DAC '89 Paper Acceptance Rate 156 of 465 submissions, 34%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Citations

Cited By

Mendler Mvon Hanxleden RTraulsen CBenini LDe Micheli GAl-Hashimi BMueller W(2009)WCRT algebra and interfaces for Esterel-style synchronous processingProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874644(93-98)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874644
Mendler Mvon Hanxleden RTraulsen C(2009)WCRT algebra and interfaces for esterel-style synchronous processing2009 Design, Automation & Test in Europe Conference & Exhibition10.1109/DATE.2009.5090639(93-98)Online publication date: Apr-2009
https://doi.org/10.1109/DATE.2009.5090639
Liu LChen HDu D(2006)The calculation of signal stable ranges in combinational circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.29803713:8(1016-1023)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.298037
Hahn WHagerer AHerrmann CMermet J(1994)Compiled-code-based simulation with timing verificationProceedings of the conference on European design automation10.5555/198174.198285(362-367)Online publication date: 23-Sep-1994
https://dl.acm.org/doi/10.5555/198174.198285
Abdallah NKiani PHajjar A(1994)New algorithms for static and dynamic sensitization of paths in timing analysisProceedings of 26th Southeastern Symposium on System Theory10.1109/SSST.1994.287847(385-389)Online publication date: 1994
https://doi.org/10.1109/SSST.1994.287847
Yang HHolburn DAmbler TJess JDe Man H(1991)A hierarchical approach to timing verification in CMOS VLSI designProceedings of the conference on European design automation10.5555/951513.951571(266-270)Online publication date: 25-Feb-1991
https://dl.acm.org/doi/10.5555/951513.951571
Yang HHolburn D(1991)A hierarchical approach to timing verification in CMOS VLSI designProceedings of the European Conference on Design Automation.10.1109/EDAC.1991.206405(266-270)Online publication date: 1991
https://doi.org/10.1109/EDAC.1991.206405
Cavin RHilbert J(1990)Design of integrated circuits: directions and challengesProceedings of the IEEE10.1109/5.5221978:2(418-435)Online publication date: Jan-1990
https://doi.org/10.1109/5.52219
Benkoski JStrojwas A(1989)Computation of delay defect and delay fault probabilities using a statistical timing simulatorProceedings. 'Meeting the Tests of Time'., International Test Conference10.1109/TEST.1989.82289(153-160)Online publication date: 1989
https://doi.org/10.1109/TEST.1989.82289
Benkoski JChew MStrojwas A(1989)A new multi-level timing simulation environment for timing verification1989 Proceedings of the IEEE Custom Integrated Circuits Conference10.1109/CICC.1989.56746(13.2/1-13.2/4)Online publication date: 1989
https://doi.org/10.1109/CICC.1989.56746

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