Article

Automatic layout of silicon-on-silicon hybrid packages

Authors:

B. Preas,

M. Pedram,

D. CurryAuthors Info & Claims

DAC '89: Proceedings of the 26th ACM/IEEE Design Automation Conference

Pages 394 - 399

https://doi.org/10.1145/74382.74448

Published: 01 June 1989 Publication History

Abstract

In modern, high speed computer systems, performance and density limits are being set more by interconnection and packaging constraints than by transistor characteristics. The most severe limitation comes from the single-chip packages that carry the VLSI circuits. Multichip, silicon-on-silicon hybrid packages can significantly improve performance by eliminating this level of packaging. A system has been developed to automatically generate hybrid layouts given a schematic description and layouts of the VLSI circuits. This paper describes the hybrid technology, the design automation system foundation, and the hybrid layout system. This layout method, in combination with the fabrication technology, produces layouts that are 5 to 8 times more dense than the same circuits implemented with single-chip packages on printed circuit boards. Simulations show that clock speeds can be increased by a factor of two.

Cited By

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Cho JSarrafzadeh M(2006)Four-bend top-down global routingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.72031617:9(793-802)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.720316
Khoo KCong J(2006)An efficient multilayer MCM router based on four-via routingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.46634314:10(1277-1290)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.466343
Carothers JDonghui Li (1999)The MCG autorouter for multichip modulesIEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications10.1109/81.76292246:5(572-578)Online publication date: May-1999
https://doi.org/10.1109/81.762922
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Index Terms

Automatic layout of silicon-on-silicon hybrid packages
1. Hardware

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Information & Contributors

Information

Published In

DAC '89: Proceedings of the 26th ACM/IEEE Design Automation Conference

June 1989

839 pages

ISBN:0897913108

DOI:10.1145/74382

Chairman:
Donald E. Thomas
Carnegie Mellon Univ., Pittsburgh, PA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 1989

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Article

Conference

DAC89

Sponsor:

IEEE-CS\TCDA
SIGDA

DAC89: The 26th ACM/IEEE-CS Design Automation Conference

June 25 - 28, 1989

Nevada, Las Vegas, USA

Acceptance Rates

DAC '89 Paper Acceptance Rate 156 of 465 submissions, 34%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

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Cited By

View all

Cho JSarrafzadeh M(2006)Four-bend top-down global routingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.72031617:9(793-802)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.720316
Khoo KCong J(2006)An efficient multilayer MCM router based on four-via routingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.46634314:10(1277-1290)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.466343
Carothers JDonghui Li (1999)The MCG autorouter for multichip modulesIEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications10.1109/81.76292246:5(572-578)Online publication date: May-1999
https://doi.org/10.1109/81.762922
Cho JSarrafzadeh M(1999)Vlsi Circuit LayoutWiley Encyclopedia of Electrical and Electronics Engineering10.1002/047134608X.W1801Online publication date: 27-Dec-1999
https://doi.org/10.1002/047134608X.W1801
Carothers JLi DHameenanttila T(1996)MCGProceedings of the 7th IEEE International Workshop on Rapid System Prototyping (RSP '96)10.5555/827259.828065Online publication date: 19-Jun-1996
https://dl.acm.org/doi/10.5555/827259.828065
Carothers JDonghui Li Hameenanttila T(1996)MCG: a correct-by-design multichip module router with crosstalk avoidanceProceedings Seventh IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype10.1109/IWRSP.1996.506804(183-188)Online publication date: 1996
https://doi.org/10.1109/IWRSP.1996.506804
Hameenanttila TCarothers JLi D(1996)Fast coupled noise estimation for crosstalk avoidance in the MCG multichip module autorouterIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/92.5320364:3(356-368)Online publication date: 1-Sep-1996
https://dl.acm.org/doi/10.1109/92.532036
Carothers JLi D(1995)A multilayer MCM autorouter based on the correct-by-design approachProceedings of Eighth International Application Specific Integrated Circuits Conference10.1109/ASIC.1995.580700(139-142)Online publication date: 1995
https://doi.org/10.1109/ASIC.1995.580700
Qiong Yu Sandeep BSherwani N(1994)CD3D: A Constraint-driven 3-dimensional Router for Thick Film McmsProceedings of the International Conference on Multichip Modules10.1109/ICMCM.1994.753606(561-566)Online publication date: 1994
https://doi.org/10.1109/ICMCM.1994.753606
Qiong Yu Sandeep BJian-Lin Lai Sherwani N(1994)A performance-driven routing approach for thick film MCMsProceedings of IEEE Custom Integrated Circuits Conference - CICC '9410.1109/CICC.1994.379638(655-658)Online publication date: 1994
https://doi.org/10.1109/CICC.1994.379638
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Trends in Silicon-On-Silicon Multichip Modules

Optimization of negative gate networks realized in weinberger-LIKF layout in a boolean level silicon compiler

Buried silicon-Germanium pMOSFETs: experimental analysis in VLSI logic circuits under aggressive voltage scaling