Article

Free access

A deterministic approach to adjacency testing for delay faults

Authors:

M. R. MercerAuthors Info & Claims

DAC '89: Proceedings of the 26th ACM/IEEE Design Automation Conference

Pages 351 - 356

https://doi.org/10.1145/74382.74441

Published: 01 June 1989 Publication History

Abstract

Adjacency testing for delay faults is examined in both theory and implementation. We shall show that the necessary and sufficient conditions for adjacency testability yield an efficient method of robust delay test generation. Empirical results (including several different cost measurements) are presented which demonstrate that our technique: (1) achieves high fault coverages under both the robust and nonrobust delay fault models and (2) is cost effective.

References

[1]

G.L. Craig and C.R. Kime, "Psuedo-Exhaustive Adjacency Testing: A BIST Approach for Stuck-Open Faults," IEEE Int'l Test Conf__, pp. 126-137, 1985.

[2]

C.T. Glover and M.R. Mercer,"A Method of Delay Fault Test Generation," 25th Design Automat. Conf., pp. 90-96,1988.

Digital Library

[3]

C.C. Liaw, S.Y. Su, and Y.K. Malaiya,"Test Generation for Delay Faults Using Stuck-at-FaultTest Set," IEEE Int'l Test Conf., pp.167-175, 1980.

[4]

C.J. Lin and S.M. Reddy,"On Delay Fault Testing in Logic Circuits," IEEE Trans. Computer-Aided Design, pp. 694-703, Sept. 1987.

[5]

Y. Levendel and P.R. Menon,"Transition Faults in Combinational Circuits" Input Transition Test Generation and Fault Simulation," 15tin FaultTolerant Comp. Syrup., pp.278-283,1986.

[6]

T. Hayashi, K. Hatayama, K. Sato, and T. Natabe,"A Delay Test Generator for Logic LSI," 14th Fault Tolerant Comp. Syrup, pp. 146-149, 1984.

[7]

K. Kishida, F. Shirotori, Y. Ikemoto, S. Ishiyama, and T. Hayashi,"A Delay Test System for High Speed Logic LSI's,"23rd Design Automat. Conf., pp. 786-790, 1986.

Digital Library

[8]

E.S. Park and M.R. Mercer,"Robust and Nonrobust Tests for Path Delay Faults in a Combinational Circuit;" IEEE Int'l Test pp. 1027-1034, 1987.

[9]

J.A. Waicukauski, E. Lindbloom, B. Rosen, and V. Iyengar,"Transition Fault Simulation by Parallel Pattern Single Fault Propagation,"IEEE {nt'l Test Conf., pp. 560-571, 1986.

[10]

Z. Barzilai and B. Rosen,"Comparison of AC Self-Testing Procedures," IEEE lnt'l Test Conf., pp. 89-94, 1983.

[11]

M.H. Sehulz and F. Berglez,"Accelerated Transition Fault Simulation," 24th Design Automat. Conf., pp. 237-243, I987.

Digital Library

[12]

G.L. Smith,"Model for Delay Faults Based Upon Paths," 1EEE Infl Test Conf. pp. 342-349, 1985.

[13]

Rajski and H. Cox,"A Method of Test Generation and Fault Diagnosis in Very Large Circuits," IEEE Int'lTest Conf., pp. 932- 943, 1987.

[14]

C.T. Glover,"Efficient Delay Fault Tes:t Generation and Simulation," Ph.D. dissertation under preparation, Dep. Elec. Comp. Eng., Univ. of Texas at Austin.

[15]

j.P. Roth,"Diagnosis of Automata Failures: a Calculus and a Method," IBM Journal of Res. andDev., vol. 10, pp. 278-291, 1966.

Digital Library

[16]

P. Goel,"An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits," IEEE Trans. Comp., pp. 215-222, March 1981.

Digital Library

Cited By

Mao WCiletti M(2006)Reducing correlation to improve coverage of delay faults in scan-path designIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.27763813:5(638-646)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.277638
Devadas SKeutzer K(2006)Validatable nonrobust delay-fault testable circuits via logic synthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.18026711:12(1559-1573)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.180267
Park EMercer M(2006)An efficient delay test generation system for combinational logic circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.14485711:7(926-938)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.144857
Show More Cited By

Index Terms

A deterministic approach to adjacency testing for delay faults
1. Hardware
  1. Hardware test
    1. Design for testability
    2. Test-pattern generation and fault simulation
  2. Very large scale integration design

Recommendations

On testing of delay faults in logic circuits
Deterministic broadside test generation for transition path delay faults
GLSVLSI '10: Proceedings of the 20th symposium on Great lakes symposium on VLSI

A deterministic broadside test generation procedure is proposed for transition path delay faults. Under this fault model, a path delay fault is detected if and only if all the individual transition faults along the path are detected by the same test. ...
Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation

In delay fault BIST (Built-In-Self-Test), an adjacency test pattern generation scheme effectively generates robust test patterns. The traditional adjacency test pattern generation schemes use LFSR to generate first patterns, and thus they cannot ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '89: Proceedings of the 26th ACM/IEEE Design Automation Conference

June 1989

839 pages

ISBN:0897913108

DOI:10.1145/74382

Chairman:
Donald E. Thomas
Carnegie Mellon Univ., Pittsburgh, PA

Copyright © 1989 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

IEEE-CS\TCDA: TC Design Automation
SIGDA: ACM Special Interest Group on Design Automation

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 1989

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

DAC89

Sponsor:

IEEE-CS\TCDA
SIGDA

DAC89: The 26th ACM/IEEE-CS Design Automation Conference

June 25 - 28, 1989

Nevada, Las Vegas, USA

Acceptance Rates

DAC '89 Paper Acceptance Rate 156 of 465 submissions, 34%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

21
Total Citations
View Citations
234
Total Downloads

Downloads (Last 12 months)46
Downloads (Last 6 weeks)8

Reflects downloads up to 16 Feb 2025

Other Metrics

View Author Metrics

Citations

Cited By

Mao WCiletti M(2006)Reducing correlation to improve coverage of delay faults in scan-path designIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.27763813:5(638-646)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.277638
Devadas SKeutzer K(2006)Validatable nonrobust delay-fault testable circuits via logic synthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.18026711:12(1559-1573)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.180267
Park EMercer M(2006)An efficient delay test generation system for combinational logic circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.14485711:7(926-938)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.144857
Devadas SKeutzer K(2006)Synthesis of robust delay-fault-testable circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.10862211:1(87-101)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.108622
Meyer VAnheier WSticht A(2001)Non-robust delay test pattern generation based on stuck-at TPGICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)10.1109/ICECS.2001.957645(1007-1010)Online publication date: 2001
https://doi.org/10.1109/ICECS.2001.957645
Virazel ADavid RGirard PLandrault CPravossoudovitch S(2001)Delay Fault TestingJournal of Electronic Testing: Theory and Applications10.1023/A:101225922762217:3-4(233-241)Online publication date: 1-Jun-2001
https://dl.acm.org/doi/10.1023/A%3A1012259227622
Crepaux-Motte SJacomino MDavid R(1996)An algebraic method for delay fault testingProceedings of 14th VLSI Test Symposium10.1109/VTEST.1996.510873(308-315)Online publication date: 1996
https://doi.org/10.1109/VTEST.1996.510873
Ryan C(1995)Bridging fault simulation using Iddq, logic, and delay testingConference Record AUTOTESTCON '95. 'Systems Readiness: Test Technology for the 21st Century'10.1109/AUTEST.1995.522670(176-180)Online publication date: 1995
https://doi.org/10.1109/AUTEST.1995.522670
Ryan C(1995)On the complexity of bridging fault simulation techniques for CMOS integrated circuitsProceedings of Eighth International Application Specific Integrated Circuits Conference10.1109/ASIC.1995.580705(160-163)Online publication date: 1995
https://doi.org/10.1109/ASIC.1995.580705
Varma P(1994)On path delay testing in a standard scan environmentProceedings., International Test Conference10.1109/TEST.1994.527947(164-173)Online publication date: 1994
https://doi.org/10.1109/TEST.1994.527947
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Figures

Tables

Media

View Table of Conten