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Automatic tub region generation for symbolic layout compaction

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C.-Y. LoAuthors Info & Claims

DAC '89: Proceedings of the 26th ACM/IEEE Design Automation Conference

Pages 302 - 306

https://doi.org/10.1145/74382.74433

Published: 01 June 1989 Publication History

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Abstract

This paper describes a new algorithm that automatically generates tub regions for VLSI symbolic layouts with quality comparable to that of human designers. The algorithm supports an explicit modeling of enclosure rules in the layout compaction task with the benefit of robustness and reduced output database size. In addition, the algorithm runs at O(n²) time and O(n) space with the expected run time of O(nlogn).

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Cited By

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Boyer DSchweikert D(1992)Process independent constraint graph compactionProceedings of the 29th ACM/IEEE Design Automation Conference10.5555/113938.149470(318-322)Online publication date: 1-Jul-1992
https://dl.acm.org/doi/10.5555/113938.149470
Boyer D(1992)Process independent constraint graph compaction[1992] Proceedings 29th ACM/IEEE Design Automation Conference10.1109/DAC.1992.227786(318-322)Online publication date: 1992
https://doi.org/10.1109/DAC.1992.227786
Pei-Yung Hsiao Wu-Shiung Feng (1990)Using a multiple storage quad tree on a hierarchical VLSI compaction schemeIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.551829:5(522-536)Online publication date: May-1990
https://doi.org/10.1109/43.55182

Index Terms

Automatic tub region generation for symbolic layout compaction
1. Hardware
  1. Electronic design automation
    1. Logic synthesis
      1. Circuit optimization
    2. Physical design (EDA)
      1. Partitioning and floorplanning
  2. Very large scale integration design

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Symbolic layout and compaction is reaching a mature status. This is demonstrated, in part, by the recent or imminent introductions of a number of commercial symbolic layout and compaction systems. The two most frequently used symbolic layout compaction ...
New approaches for VLSI layout compaction

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Published In

DAC '89: Proceedings of the 26th ACM/IEEE Design Automation Conference

June 1989

839 pages

ISBN:0897913108

DOI:10.1145/74382

Chairman:
Donald E. Thomas
Carnegie Mellon Univ., Pittsburgh, PA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 01 June 1989

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DAC89: The 26th ACM/IEEE-CS Design Automation Conference

June 25 - 28, 1989

Nevada, Las Vegas, USA

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DAC '89 Paper Acceptance Rate 156 of 465 submissions, 34%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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Boyer DSchweikert D(1992)Process independent constraint graph compactionProceedings of the 29th ACM/IEEE Design Automation Conference10.5555/113938.149470(318-322)Online publication date: 1-Jul-1992
https://dl.acm.org/doi/10.5555/113938.149470
Boyer D(1992)Process independent constraint graph compaction[1992] Proceedings 29th ACM/IEEE Design Automation Conference10.1109/DAC.1992.227786(318-322)Online publication date: 1992
https://doi.org/10.1109/DAC.1992.227786
Pei-Yung Hsiao Wu-Shiung Feng (1990)Using a multiple storage quad tree on a hierarchical VLSI compaction schemeIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.551829:5(522-536)Online publication date: May-1990
https://doi.org/10.1109/43.55182

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Recommendations

Techniques for IC symbolic layout and compaction

Symbolic layout compaction review

New approaches for VLSI layout compaction