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Pixel-planes 5: a heterogeneous multiprocessor graphics system using processor-enhanced memories

Published: 01 July 1989 Publication History

Abstract

This paper introduces the architecture and initial algorithms for Pixel-Planes 5, a heterogeneous multi-computer designed both for high-speed polygon and sphere rendering (1M Phong-shaded triangles/second) and for supporting algorithm and application research in interactive 3D graphics. Techniques are described for volume rendering at multiple frames per second, font generation directly from conic spline descriptions, and rapid calculation of radiosity form-factors. The hardware consists of up to 32 math-oriented processors, up to 16 rendering units, and a conventional 1280 × 1024-pixel frame buffer, interconnected by a 5 gigabit ring network. Each rendering unit consists of a 128 × 128-pixel array of processors-with-memory with parallel quadratic expression evaluation for every pixel. Implemented on 1.6 micron CMOS chips designed to run at 40MHz, this array has 208 bits/pixel on-chip and is connected to a video RAM memory system that provides 4,096 bits of off-chip memory. Rendering units can be independently reasigned to any part of the screen or to non-screen-oriented computation. As of April 1989, both hardware and software are still under construction, with initial system operation scheduled for fall 1989.

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Information

Published In

cover image ACM SIGGRAPH Computer Graphics
ACM SIGGRAPH Computer Graphics  Volume 23, Issue 3
Special issue: Proceedings of the 1989 ACM SIGGRAPH conference
July 1989
367 pages
ISSN:0097-8930
DOI:10.1145/74334
Issue’s Table of Contents
  • cover image ACM Conferences
    SIGGRAPH '89: Proceedings of the 16th annual conference on Computer graphics and interactive techniques
    July 1989
    408 pages
    ISBN:0897913124
    DOI:10.1145/74333
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 01 July 1989
Published in SIGGRAPH Volume 23, Issue 3

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  • (2022)DTexL: Decoupled Raster Pipeline for Texture LocalityProceedings of the 55th Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO56248.2022.00028(213-227)Online publication date: 1-Oct-2022
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