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Performance measurements on a commercial multiprocessor running parallel code

Authors:

R. RühlAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 17, Issue 3

Pages 307 - 314

https://doi.org/10.1145/74926.74960

Published: 01 April 1989 Publication History

Abstract

The multiprocessor Sequent Symmetry was first delivered to customers with write-through caches. Later on each machine was upgraded with copy-back caches. Because all the other architectural parameters were unchanged (main memory, bus, cache organization and size, and so on), this made it possible to measure the performance of a multiprocessor with no caches, write-through caches, and copy-back caches. We also study the impact that the language (FORTRAN and C) has on the performance of the machine.

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Cited By

Terasawa TInoue KKurosawa HAmano H(1997)A study on snoop cache systems for single-chip multiprocessorsSystems and Computers in Japan10.1002/(SICI)1520-684X(199702)28:2<62::AID-SCJ7>3.0.CO;2-P28:2(62-72)Online publication date: Feb-1997
https://doi.org/10.1002/(SICI)1520-684X(199702)28:2<62::AID-SCJ7>3.0.CO;2-P
Clapp RMudge TWinsor D(1990)Cache coherence requirements for interprocess rendezvousInternational Journal of Parallel Programming10.1007/BF0140786319:1(31-51)Online publication date: 1-Oct-1990
https://dl.acm.org/doi/10.1007/BF01407863

Index Terms

Performance measurements on a commercial multiprocessor running parallel code

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Special issue: high performance computing systems

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Information & Contributors

Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 17, Issue 3

Special Issue: Proceedings of the 16th annual international symposium on Computer Architecture

June 1989

400 pages

ISSN:0163-5964

DOI:10.1145/74926

Editor:
Jean-Claude Syre

Issue’s Table of Contents

ISCA '89: Proceedings of the 16th annual international symposium on Computer architecture
April 1989
426 pages
ISBN:0897913191
DOI:10.1145/74925
Chairman:
Jean-Claude Syre

Copyright © 1989 Authors.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 April 1989

Published in SIGARCH Volume 17, Issue 3

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Cited By

Terasawa TInoue KKurosawa HAmano H(1997)A study on snoop cache systems for single-chip multiprocessorsSystems and Computers in Japan10.1002/(SICI)1520-684X(199702)28:2<62::AID-SCJ7>3.0.CO;2-P28:2(62-72)Online publication date: Feb-1997
https://doi.org/10.1002/(SICI)1520-684X(199702)28:2<62::AID-SCJ7>3.0.CO;2-P
Clapp RMudge TWinsor D(1990)Cache coherence requirements for interprocess rendezvousInternational Journal of Parallel Programming10.1007/BF0140786319:1(31-51)Online publication date: 1-Oct-1990
https://dl.acm.org/doi/10.1007/BF01407863

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