Using an architectural knowledge base to generate code for parallel computers

Reviewer: Michael Wolfe

The authors present a reconfigurable compiler for distributed memory parallel computers. Like similar projects underway elsewhere, this compiler presents the user with a single address space programming model; the user also annotates the program with directives to guide the partitioning phase. The compiler then automatically distributes the data arrays onto a distributed memory processor system and maps the computation and communication onto the processors. The unique element of this project is the use of Prolog in the two code generators. The first code generator partitions data and generates code for control flow, using appropriate rules describing the parallel system architecture. The second code generator generates code for the computation (like a sequential code generator) and uses Prolog rules describing the detailed processor architecture. The bulk of the paper describes the code generated for two examples (iterative solution of a PDE and an FFT). The authors do not describe the types of rules used in the compiler or the level of effort needed to port the compiler to a new architecture. No references to other published work on this project are given. This paper is a reasonable high-level introduction to this project but does not give nearly enough specifics to satisfy any detailed interest in the subject matter.